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usb: gadget: mv_udc: refine the driver structure
This patch do the following things: 1. Add header and Copyright for marvell usb driver. 2. Add mv_usb.h in include/linux/platform_data, make the driver fits all the marvell platform using the same ChipIdea usb ip. 3. Some SOC may has mutiple clock sources, so let me define it in mv_usb_platform_data and give two helper functions named udc_clock_enable/udc_clock_disable to deal with the clocks. 4. Different SOCs will have some difference in PHY initialization, so we will remove file mv_udc_phy.c and add two funtions in mv_usb_platform_data, let the platform relative driver to realize it. 5. Rewrite probe function according to the modification list above. Find it will kernel panic when probe failed. The root cause is as follows: When probe failed, the error handle may call device_unregister() which in return will call gadget_release.In current code, gadget_release have two issues: 1: the_controller is a NULL pointer. 2: if we free udc here, then the following code in probe will access NULL pointer. Signed-off-by: Neil Zhang <zhangwm@marvell.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Neil Zhang
Felipe Balbi
parent
8a9775ab71
commit
dde34cc501
@ -28,7 +28,7 @@ obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
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obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
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obj-$(CONFIG_USB_EG20T) += pch_udc.o
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obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
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mv_udc-y := mv_udc_core.o mv_udc_phy.o
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mv_udc-y := mv_udc_core.o
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obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
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obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
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@ -1,3 +1,11 @@
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/*
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MV_UDC_H
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#define __MV_UDC_H
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@ -201,7 +209,12 @@ struct mv_udc {
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remote_wakeup:1,
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softconnected:1,
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force_fs:1;
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struct clk *clk;
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struct mv_usb_platform_data *pdata;
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/* some SOC has mutiple clock sources for USB*/
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unsigned int clknum;
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struct clk *clk[0];
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};
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/* endpoint data structure */
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@ -289,6 +302,4 @@ struct mv_dtd {
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struct mv_dtd *next_dtd_virt;
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};
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extern int mv_udc_phy_init(unsigned int base);
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#endif
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@ -1,3 +1,14 @@
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/*
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
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* Author: Chao Xie <chao.xie@marvell.com>
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* Neil Zhang <zhangwm@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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@ -22,6 +33,7 @@
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/platform_data/mv_usb.h>
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#include <asm/system.h>
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#include <asm/unaligned.h>
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@ -45,6 +57,8 @@
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#define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
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#define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
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static DECLARE_COMPLETION(release_done);
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static const char driver_name[] = "mv_udc";
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static const char driver_desc[] = DRIVER_DESC;
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@ -987,6 +1001,22 @@ static struct usb_ep_ops mv_ep_ops = {
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.fifo_flush = mv_ep_fifo_flush, /* flush fifo */
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};
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static void udc_clock_enable(struct mv_udc *udc)
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{
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unsigned int i;
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for (i = 0; i < udc->clknum; i++)
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clk_enable(udc->clk[i]);
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}
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static void udc_clock_disable(struct mv_udc *udc)
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{
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unsigned int i;
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for (i = 0; i < udc->clknum; i++)
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clk_disable(udc->clk[i]);
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}
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static void udc_stop(struct mv_udc *udc)
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{
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u32 tmp;
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@ -1877,18 +1907,15 @@ static void gadget_release(struct device *_dev)
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struct mv_udc *udc = the_controller;
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complete(udc->done);
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kfree(udc);
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}
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static int mv_udc_remove(struct platform_device *dev)
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{
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struct mv_udc *udc = the_controller;
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DECLARE_COMPLETION(done);
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int clk_i;
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usb_del_gadget_udc(&udc->gadget);
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udc->done = &done;
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/* free memory allocated in probe */
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if (udc->dtd_pool)
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dma_pool_destroy(udc->dtd_pool);
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@ -1915,10 +1942,14 @@ static int mv_udc_remove(struct platform_device *dev)
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kfree(udc->status_req);
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}
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for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
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clk_put(udc->clk[clk_i]);
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device_unregister(&udc->gadget.dev);
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/* free dev, wait for the release() finished */
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wait_for_completion(&done);
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wait_for_completion(udc->done);
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kfree(udc);
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the_controller = NULL;
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@ -1927,33 +1958,46 @@ static int mv_udc_remove(struct platform_device *dev)
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int mv_udc_probe(struct platform_device *dev)
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{
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struct mv_usb_platform_data *pdata = dev->dev.platform_data;
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struct mv_udc *udc;
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int retval = 0;
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int clk_i = 0;
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struct resource *r;
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size_t size;
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udc = kzalloc(sizeof *udc, GFP_KERNEL);
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if (udc == NULL) {
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dev_err(&dev->dev, "failed to allocate memory for udc\n");
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retval = -ENOMEM;
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goto error;
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if (pdata == NULL) {
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dev_err(&dev->dev, "missing platform_data\n");
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return -ENODEV;
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}
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size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
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udc = kzalloc(size, GFP_KERNEL);
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if (udc == NULL) {
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dev_err(&dev->dev, "failed to allocate memory for udc\n");
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return -ENOMEM;
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}
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the_controller = udc;
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udc->done = &release_done;
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udc->pdata = dev->dev.platform_data;
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spin_lock_init(&udc->lock);
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udc->dev = dev;
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udc->clk = clk_get(&dev->dev, "U2OCLK");
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if (IS_ERR(udc->clk)) {
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retval = PTR_ERR(udc->clk);
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goto error;
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udc->clknum = pdata->clknum;
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for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
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udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
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if (IS_ERR(udc->clk[clk_i])) {
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retval = PTR_ERR(udc->clk[clk_i]);
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goto err_put_clk;
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}
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}
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r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2o");
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r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
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if (r == NULL) {
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dev_err(&dev->dev, "no I/O memory resource defined\n");
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retval = -ENODEV;
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goto error;
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goto err_put_clk;
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}
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udc->cap_regs = (struct mv_cap_regs __iomem *)
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@ -1961,29 +2005,31 @@ int mv_udc_probe(struct platform_device *dev)
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if (udc->cap_regs == NULL) {
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dev_err(&dev->dev, "failed to map I/O memory\n");
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retval = -EBUSY;
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goto error;
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goto err_put_clk;
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}
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r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2ophy");
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r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
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if (r == NULL) {
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dev_err(&dev->dev, "no phy I/O memory resource defined\n");
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retval = -ENODEV;
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goto error;
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goto err_iounmap_capreg;
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}
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udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
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if (udc->phy_regs == 0) {
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dev_err(&dev->dev, "failed to map phy I/O memory\n");
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retval = -EBUSY;
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goto error;
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goto err_iounmap_capreg;
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}
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/* we will acces controller register, so enable the clk */
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clk_enable(udc->clk);
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retval = mv_udc_phy_init(udc->phy_regs);
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if (retval) {
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dev_err(&dev->dev, "phy initialization error %d\n", retval);
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goto error;
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udc_clock_enable(udc);
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if (pdata->phy_init) {
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retval = pdata->phy_init(udc->phy_regs);
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if (retval) {
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dev_err(&dev->dev, "phy init error %d\n", retval);
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goto err_iounmap_phyreg;
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}
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}
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udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
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@ -1999,7 +2045,7 @@ int mv_udc_probe(struct platform_device *dev)
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if (udc->ep_dqh == NULL) {
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dev_err(&dev->dev, "allocate dQH memory failed\n");
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retval = -ENOMEM;
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goto error;
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goto err_disable_clock;
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}
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udc->ep_dqh_size = size;
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@ -2012,7 +2058,7 @@ int mv_udc_probe(struct platform_device *dev)
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if (!udc->dtd_pool) {
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retval = -ENOMEM;
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goto error;
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goto err_free_dma;
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}
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size = udc->max_eps * sizeof(struct mv_ep) *2;
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@ -2020,7 +2066,7 @@ int mv_udc_probe(struct platform_device *dev)
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if (udc->eps == NULL) {
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dev_err(&dev->dev, "allocate ep memory failed\n");
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retval = -ENOMEM;
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goto error;
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goto err_destroy_dma;
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}
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/* initialize ep0 status request structure */
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@ -2028,7 +2074,7 @@ int mv_udc_probe(struct platform_device *dev)
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if (!udc->status_req) {
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dev_err(&dev->dev, "allocate status_req memory failed\n");
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retval = -ENOMEM;
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goto error;
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goto err_free_eps;
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}
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INIT_LIST_HEAD(&udc->status_req->queue);
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@ -2045,7 +2091,7 @@ int mv_udc_probe(struct platform_device *dev)
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if (r == NULL) {
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dev_err(&dev->dev, "no IRQ resource defined\n");
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retval = -ENODEV;
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goto error;
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goto err_free_status_req;
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}
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udc->irq = r->start;
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if (request_irq(udc->irq, mv_udc_irq,
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@ -2053,7 +2099,7 @@ int mv_udc_probe(struct platform_device *dev)
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dev_err(&dev->dev, "Request irq %d for UDC failed\n",
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udc->irq);
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retval = -ENODEV;
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goto error;
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goto err_free_status_req;
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}
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/* initialize gadget structure */
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@ -2072,18 +2118,43 @@ int mv_udc_probe(struct platform_device *dev)
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retval = device_register(&udc->gadget.dev);
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if (retval)
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goto error;
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goto err_free_irq;
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eps_init(udc);
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the_controller = udc;
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retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
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if (!retval)
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return retval;
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error:
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if (udc)
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mv_udc_remove(udc->dev);
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if (retval)
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goto err_unregister;
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return 0;
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err_unregister:
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device_unregister(&udc->gadget.dev);
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err_free_irq:
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free_irq(udc->irq, &dev->dev);
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err_free_status_req:
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kfree(udc->status_req->req.buf);
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kfree(udc->status_req);
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err_free_eps:
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kfree(udc->eps);
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err_destroy_dma:
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dma_pool_destroy(udc->dtd_pool);
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err_free_dma:
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dma_free_coherent(&dev->dev, udc->ep_dqh_size,
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udc->ep_dqh, udc->ep_dqh_dma);
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err_disable_clock:
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if (udc->pdata->phy_deinit)
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udc->pdata->phy_deinit(udc->phy_regs);
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udc_clock_disable(udc);
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err_iounmap_phyreg:
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iounmap((void *)udc->phy_regs);
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err_iounmap_capreg:
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iounmap(udc->cap_regs);
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err_put_clk:
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for (clk_i--; clk_i >= 0; clk_i--)
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clk_put(udc->clk[clk_i]);
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the_controller = NULL;
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kfree(udc);
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return retval;
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}
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@ -2102,11 +2173,16 @@ static int mv_udc_resume(struct device *_dev)
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struct mv_udc *udc = the_controller;
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int retval;
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retval = mv_udc_phy_init(udc->phy_regs);
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if (retval) {
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dev_err(_dev, "phy initialization error %d\n", retval);
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return retval;
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if (udc->pdata->phy_init) {
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retval = udc->pdata->phy_init(udc->phy_regs);
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if (retval) {
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dev_err(&udc->dev->dev,
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"init phy error %d when resume back\n",
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retval);
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return retval;
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}
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}
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udc_reset(udc);
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ep0_reset(udc);
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udc_start(udc);
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@ -1,214 +0,0 @@
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <mach/cputype.h>
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#ifdef CONFIG_ARCH_MMP
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#define UTMI_REVISION 0x0
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#define UTMI_CTRL 0x4
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#define UTMI_PLL 0x8
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#define UTMI_TX 0xc
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#define UTMI_RX 0x10
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#define UTMI_IVREF 0x14
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#define UTMI_T0 0x18
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#define UTMI_T1 0x1c
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#define UTMI_T2 0x20
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#define UTMI_T3 0x24
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#define UTMI_T4 0x28
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#define UTMI_T5 0x2c
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#define UTMI_RESERVE 0x30
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#define UTMI_USB_INT 0x34
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#define UTMI_DBG_CTL 0x38
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#define UTMI_OTG_ADDON 0x3c
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|
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/* For UTMICTRL Register */
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#define UTMI_CTRL_USB_CLK_EN (1 << 31)
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/* pxa168 */
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#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
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#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
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#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
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#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
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#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
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#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
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#define UTMI_CTRL_PU_REF_SHIFT 20
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#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
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#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
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#define UTMI_CTRL_PWR_UP_SHIFT 0
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/* For UTMI_PLL Register */
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#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
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#define UTMI_PLL_FBDIV_SHIFT 4
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#define UTMI_PLL_REFDIV_SHIFT 0
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#define UTMI_PLL_FBDIV_MASK 0x00000FF0
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#define UTMI_PLL_REFDIV_MASK 0x0000000F
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#define UTMI_PLL_ICP_MASK 0x00007000
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#define UTMI_PLL_KVCO_MASK 0x00031000
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#define UTMI_PLL_PLLCALI12_SHIFT 29
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#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
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#define UTMI_PLL_PLLVDD18_SHIFT 27
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#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
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#define UTMI_PLL_PLLVDD12_SHIFT 25
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#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
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#define UTMI_PLL_KVCO_SHIFT 15
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#define UTMI_PLL_ICP_SHIFT 12
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/* For UTMI_TX Register */
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#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
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#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
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#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK 26
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#define UTMI_TX_REG_EXT_FS_RCAL_EN (0x1 << 26)
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#define UTMI_TX_LOW_VDD_EN_SHIFT 11
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#define UTMI_TX_IMPCAL_VTH_SHIFT 14
|
||||
#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
|
||||
#define UTMI_TX_CK60_PHSEL_SHIFT 17
|
||||
#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
|
||||
#define UTMI_TX_TXVDD12_SHIFT 22
|
||||
#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
|
||||
#define UTMI_TX_AMP_SHIFT 0
|
||||
#define UTMI_TX_AMP_MASK (0x7 << 0)
|
||||
/* For UTMI_RX Register */
|
||||
#define UTMI_RX_SQ_THRESH_SHIFT 4
|
||||
#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
|
||||
#define UTMI_REG_SQ_LENGTH_SHIFT 15
|
||||
#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
|
||||
|
||||
#define REG_RCAL_START 0x00001000
|
||||
#define VCOCAL_START 0x00200000
|
||||
#define KVCO_EXT 0x00400000
|
||||
#define PLL_READY 0x00800000
|
||||
#define CLK_BLK_EN 0x01000000
|
||||
#endif
|
||||
|
||||
static unsigned int u2o_read(unsigned int base, unsigned int offset)
|
||||
{
|
||||
return readl(base + offset);
|
||||
}
|
||||
|
||||
static void u2o_set(unsigned int base, unsigned int offset, unsigned int value)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = readl(base + offset);
|
||||
reg |= value;
|
||||
writel(reg, base + offset);
|
||||
readl(base + offset);
|
||||
}
|
||||
|
||||
static void u2o_clear(unsigned int base, unsigned int offset,
|
||||
unsigned int value)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = readl(base + offset);
|
||||
reg &= ~value;
|
||||
writel(reg, base + offset);
|
||||
readl(base + offset);
|
||||
}
|
||||
|
||||
static void u2o_write(unsigned int base, unsigned int offset,
|
||||
unsigned int value)
|
||||
{
|
||||
writel(value, base + offset);
|
||||
readl(base + offset);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_MMP
|
||||
int mv_udc_phy_init(unsigned int base)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/* Initialize the USB PHY power */
|
||||
if (cpu_is_pxa910()) {
|
||||
u2o_set(base, UTMI_CTRL, (1 << UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
|
||||
| (1 << UTMI_CTRL_PU_REF_SHIFT));
|
||||
}
|
||||
|
||||
u2o_set(base, UTMI_CTRL, 1 << UTMI_CTRL_PLL_PWR_UP_SHIFT);
|
||||
u2o_set(base, UTMI_CTRL, 1 << UTMI_CTRL_PWR_UP_SHIFT);
|
||||
|
||||
/* UTMI_PLL settings */
|
||||
u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
|
||||
| UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
|
||||
| UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
|
||||
| UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
|
||||
|
||||
u2o_set(base, UTMI_PLL, (0xee << UTMI_PLL_FBDIV_SHIFT)
|
||||
| (0xb << UTMI_PLL_REFDIV_SHIFT)
|
||||
| (3 << UTMI_PLL_PLLVDD18_SHIFT)
|
||||
| (3 << UTMI_PLL_PLLVDD12_SHIFT)
|
||||
| (3 << UTMI_PLL_PLLCALI12_SHIFT)
|
||||
| (1 << UTMI_PLL_ICP_SHIFT) | (3 << UTMI_PLL_KVCO_SHIFT));
|
||||
|
||||
/* UTMI_TX */
|
||||
u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
|
||||
| UTMI_TX_TXVDD12_MASK
|
||||
| UTMI_TX_CK60_PHSEL_MASK | UTMI_TX_IMPCAL_VTH_MASK
|
||||
| UTMI_TX_REG_EXT_FS_RCAL_MASK | UTMI_TX_AMP_MASK);
|
||||
u2o_set(base, UTMI_TX, (3 << UTMI_TX_TXVDD12_SHIFT)
|
||||
| (4 << UTMI_TX_CK60_PHSEL_SHIFT)
|
||||
| (4 << UTMI_TX_IMPCAL_VTH_SHIFT)
|
||||
| (8 << UTMI_TX_REG_EXT_FS_RCAL_SHIFT)
|
||||
| (3 << UTMI_TX_AMP_SHIFT));
|
||||
|
||||
/* UTMI_RX */
|
||||
u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
|
||||
| UTMI_REG_SQ_LENGTH_MASK);
|
||||
if (cpu_is_pxa168())
|
||||
u2o_set(base, UTMI_RX, (7 << UTMI_RX_SQ_THRESH_SHIFT)
|
||||
| (2 << UTMI_REG_SQ_LENGTH_SHIFT));
|
||||
else
|
||||
u2o_set(base, UTMI_RX, (0x7 << UTMI_RX_SQ_THRESH_SHIFT)
|
||||
| (2 << UTMI_REG_SQ_LENGTH_SHIFT));
|
||||
|
||||
/* UTMI_IVREF */
|
||||
if (cpu_is_pxa168())
|
||||
/*
|
||||
* fixing Microsoft Altair board interface with NEC hub issue -
|
||||
* Set UTMI_IVREF from 0x4a3 to 0x4bf
|
||||
*/
|
||||
u2o_write(base, UTMI_IVREF, 0x4bf);
|
||||
|
||||
/* calibrate */
|
||||
timeout = jiffies + 100;
|
||||
while ((u2o_read(base, UTMI_PLL) & PLL_READY) == 0) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIME;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/* toggle VCOCAL_START bit of UTMI_PLL */
|
||||
udelay(200);
|
||||
u2o_set(base, UTMI_PLL, VCOCAL_START);
|
||||
udelay(40);
|
||||
u2o_clear(base, UTMI_PLL, VCOCAL_START);
|
||||
|
||||
/* toggle REG_RCAL_START bit of UTMI_TX */
|
||||
udelay(200);
|
||||
u2o_set(base, UTMI_TX, REG_RCAL_START);
|
||||
udelay(40);
|
||||
u2o_clear(base, UTMI_TX, REG_RCAL_START);
|
||||
udelay(200);
|
||||
|
||||
/* make sure phy is ready */
|
||||
timeout = jiffies + 100;
|
||||
while ((u2o_read(base, UTMI_PLL) & PLL_READY) == 0) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIME;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (cpu_is_pxa168()) {
|
||||
u2o_set(base, UTMI_RESERVE, 1 << 5);
|
||||
/* Turn on UTMI PHY OTG extension */
|
||||
u2o_write(base, UTMI_OTG_ADDON, 1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int mv_udc_phy_init(unsigned int base)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
50
include/linux/platform_data/mv_usb.h
Normal file
50
include/linux/platform_data/mv_usb.h
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MV_PLATFORM_USB_H
|
||||
#define __MV_PLATFORM_USB_H
|
||||
|
||||
enum pxa_ehci_type {
|
||||
EHCI_UNDEFINED = 0,
|
||||
PXA_U2OEHCI, /* pxa 168, 9xx */
|
||||
PXA_SPH, /* pxa 168, 9xx SPH */
|
||||
MMP3_HSIC, /* mmp3 hsic */
|
||||
MMP3_FSIC, /* mmp3 fsic */
|
||||
};
|
||||
|
||||
enum {
|
||||
MV_USB_MODE_OTG,
|
||||
MV_USB_MODE_HOST,
|
||||
};
|
||||
|
||||
enum {
|
||||
VBUS_LOW = 0,
|
||||
VBUS_HIGH = 1 << 0,
|
||||
};
|
||||
|
||||
struct mv_usb_addon_irq {
|
||||
unsigned int irq;
|
||||
int (*poll)(void);
|
||||
};
|
||||
|
||||
struct mv_usb_platform_data {
|
||||
unsigned int clknum;
|
||||
char **clkname;
|
||||
struct mv_usb_addon_irq *id; /* Only valid for OTG. ID pin change*/
|
||||
struct mv_usb_addon_irq *vbus; /* valid for OTG/UDC. VBUS change*/
|
||||
|
||||
/* only valid for HCD. OTG or Host only*/
|
||||
unsigned int mode;
|
||||
|
||||
int (*phy_init)(unsigned int regbase);
|
||||
void (*phy_deinit)(unsigned int regbase);
|
||||
int (*set_vbus)(unsigned int vbus);
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user