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ARM: tegra: Core changes for v5.2-rc1
One of these patches enables PM by default on 32-bit ARM, following the same default that we already have on 64-bit ARM. The other patch fixes a cosmetic issue in the cpuidle driver for Tegra20 and Tegra30. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAly4jdcTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoRfDD/0erbE8+w+L6RjRBAfY9KefW9I7nbdm LJFiXEJOzDqjuKBsnyy+1pOs3hgLlhL/wgy1ndGNc+cUh5hdfcwlSJiWG+iyxq4q gqAQ/sBcaGkhCc+arbsQq6JPwwf3VkuxwUC4r7e7jnnOlP74NTd23PH5R9ktidgJ EiEevf1HQwQxrTcYHmUObBKoCDv5dkBe89RnLItwwE3YLWnsSkFcS+tjDdtRw6y3 lRzN6oIOMcGan+4UJMCfAHFdzBBY9ceGXZzoWwLMZRq9j6lSerl761EJT9NFlHQs 4gOXa7k0EijCcyjL6Tz/MIB5N5PqGeZkbEmSga6E4htLe3xipRMU3NcmFpzq3rsk /Ekio1HmpvWhHQknqzQvHzOeFag8Z2SRtU3HLZyoHtc5mTkYln9CsVLXcHAt843C q9hzzGUG4CDIGiu5wCLE5LFXt+MUGhFB6pVf/J0uGhNAdVfpp5lWdVC2SiW1Xwzc wGvPJyI26lisE5rqKnAxpRj3VzCU6gWBAz2Ff9VbAZ5lsGcFAeHNhFW3dL7L5ges aQyMnIIqurCI0SO49B3JKGkv7J+LI7EwENhPZrKBvrBVLaVl1B4jHHfI0A4Y+Oi3 y1Xfh2lU0M6BI5KM/Pm9lxDKhC4nzhKj9aMyZgwbrVPZXxJX4plxLQMzJCKhdTe7 uahlAQUt1dDjaQ== =u6uq -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.2-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers ARM: tegra: Core changes for v5.2-rc1 One of these patches enables PM by default on 32-bit ARM, following the same default that we already have on 64-bit ARM. The other patch fixes a cosmetic issue in the cpuidle driver for Tegra20 and Tegra30. * tag 'tegra-for-5.2-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 ARM: tegra: enforce PM requirement Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
dd3e3f2338
@ -10,6 +10,7 @@ menuconfig ARCH_TEGRA
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select PINCTRL
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select PM
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select PM_OPP
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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@ -61,7 +61,8 @@ static struct cpuidle_driver tegra_idle_driver = {
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.exit_latency = 5000,
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.target_residency = 10000,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_COUPLED,
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.flags = CPUIDLE_FLAG_COUPLED |
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CPUIDLE_FLAG_TIMER_STOP,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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@ -136,12 +137,8 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
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if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
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return false;
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tick_broadcast_enter();
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tegra_idle_lp2_last();
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tick_broadcast_exit();
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if (cpu_online(1))
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tegra20_wake_cpu1_from_reset();
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@ -153,14 +150,10 @@ static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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tick_broadcast_enter();
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cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
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tegra20_cpu_clear_resettable();
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tick_broadcast_exit();
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return true;
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}
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#else
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@ -56,6 +56,7 @@ static struct cpuidle_driver tegra_idle_driver = {
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.exit_latency = 2000,
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.target_residency = 2200,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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@ -76,12 +77,8 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
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return false;
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}
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tick_broadcast_enter();
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tegra_idle_lp2_last();
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tick_broadcast_exit();
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return true;
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}
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@ -90,14 +87,10 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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tick_broadcast_enter();
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smp_wmb();
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cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
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tick_broadcast_exit();
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return true;
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}
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#else
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