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[PATCH] chrp_pegasos_eth: Added Marvell Discovery II SRAM support
Add proper entry to support the Marvell MV64361 (Marvell Discovery II) SRAM. This feature may be used by the mv643xx_eth driver. Signed-off-by: Nicolas DET <det.nicolas@free.fr> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Nicolas DET
Paul Mackerras
parent
8c9795ba01
commit
dd03d25fac
@ -17,7 +17,20 @@
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#include <linux/mv643xx.h>
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#include <linux/pci.h>
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/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
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#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
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#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
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#define PEGASOS2_SRAM_BASE (0xf2000000)
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#define PEGASOS2_SRAM_SIZE (256*1024)
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#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
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#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
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#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
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#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
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#undef BE_VERBOSE
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static struct resource mv643xx_eth_shared_resources[] = {
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[0] = {
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.name = "ethernet shared base",
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@ -44,7 +57,16 @@ static struct resource mv643xx_eth0_resources[] = {
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},
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};
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static struct mv643xx_eth_platform_data eth0_pd;
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static struct mv643xx_eth_platform_data eth0_pd = {
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.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
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.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
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.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
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.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
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.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
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.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
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};
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static struct platform_device eth0_device = {
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.name = MV643XX_ETH_NAME,
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@ -65,7 +87,15 @@ static struct resource mv643xx_eth1_resources[] = {
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},
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};
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static struct mv643xx_eth_platform_data eth1_pd;
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static struct mv643xx_eth_platform_data eth1_pd = {
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.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
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.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
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.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
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.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
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.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
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.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
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};
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static struct platform_device eth1_device = {
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.name = MV643XX_ETH_NAME,
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@ -83,9 +113,62 @@ static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
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ð1_device,
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};
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/***********/
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/***********/
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#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
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#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
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int
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mv643xx_eth_add_pds(void)
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static void __iomem *mv643xx_reg_base;
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static int Enable_SRAM(void)
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{
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u32 ALong;
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if (mv643xx_reg_base == NULL)
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mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
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PEGASOS2_MARVELL_REGSIZE);
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if (mv643xx_reg_base == NULL)
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return -ENOMEM;
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
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(void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
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#endif
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MV_WRITE(MV64340_SRAM_CONFIG, 0);
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MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
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MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
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ALong &= ~(1 << 19);
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MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
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ALong = 0x02;
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ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
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MV_WRITE(MV643XX_ETH_BAR_4, ALong);
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MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
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MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
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ALong &= ~(1 << 4);
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MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: register unmapped\n");
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printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
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#endif
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iounmap(mv643xx_reg_base);
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mv643xx_reg_base = NULL;
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return 1;
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}
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/***********/
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/***********/
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int mv643xx_eth_add_pds(void)
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{
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int ret = 0;
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static struct pci_device_id pci_marvell_mv64360[] = {
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@ -93,9 +176,38 @@ mv643xx_eth_add_pds(void)
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{ }
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};
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: init\n");
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#endif
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if (pci_dev_present(pci_marvell_mv64360)) {
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ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
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ret = platform_add_devices(mv643xx_eth_pd_devs,
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ARRAY_SIZE(mv643xx_eth_pd_devs));
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if ( Enable_SRAM() < 0)
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{
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eth0_pd.tx_sram_addr = 0;
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eth0_pd.tx_sram_size = 0;
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eth0_pd.rx_sram_addr = 0;
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eth0_pd.rx_sram_size = 0;
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eth1_pd.tx_sram_addr = 0;
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eth1_pd.tx_sram_size = 0;
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eth1_pd.rx_sram_addr = 0;
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eth1_pd.rx_sram_size = 0;
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: Can't enable the "
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"SRAM\n");
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#endif
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}
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}
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: init is over\n");
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#endif
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return ret;
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}
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device_initcall(mv643xx_eth_add_pds);
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@ -17,7 +17,20 @@
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#include <linux/mv643xx.h>
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#include <linux/pci.h>
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/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
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#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
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#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
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#define PEGASOS2_SRAM_BASE (0xf2000000)
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#define PEGASOS2_SRAM_SIZE (256*1024)
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#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
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#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
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#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
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#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
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#undef BE_VERBOSE
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static struct resource mv643xx_eth_shared_resources[] = {
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[0] = {
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.name = "ethernet shared base",
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@ -44,7 +57,16 @@ static struct resource mv643xx_eth0_resources[] = {
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},
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};
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static struct mv643xx_eth_platform_data eth0_pd;
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static struct mv643xx_eth_platform_data eth0_pd = {
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.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
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.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
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.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
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.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
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.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
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.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
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};
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static struct platform_device eth0_device = {
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.name = MV643XX_ETH_NAME,
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@ -65,7 +87,15 @@ static struct resource mv643xx_eth1_resources[] = {
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},
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};
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static struct mv643xx_eth_platform_data eth1_pd;
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static struct mv643xx_eth_platform_data eth1_pd = {
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.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
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.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
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.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
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.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
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.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
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.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
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};
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static struct platform_device eth1_device = {
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.name = MV643XX_ETH_NAME,
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@ -83,9 +113,62 @@ static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
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ð1_device,
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};
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/***********/
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/***********/
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#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
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#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
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int
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mv643xx_eth_add_pds(void)
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static void __iomem *mv643xx_reg_base;
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static int Enable_SRAM(void)
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{
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u32 ALong;
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if (mv643xx_reg_base == NULL)
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mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
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PEGASOS2_MARVELL_REGSIZE);
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if (mv643xx_reg_base == NULL)
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return -ENOMEM;
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
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(void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
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#endif
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MV_WRITE(MV64340_SRAM_CONFIG, 0);
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MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
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MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
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ALong &= ~(1 << 19);
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MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
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ALong = 0x02;
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ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
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MV_WRITE(MV643XX_ETH_BAR_4, ALong);
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MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
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MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
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ALong &= ~(1 << 4);
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MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: register unmapped\n");
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printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
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#endif
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iounmap(mv643xx_reg_base);
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mv643xx_reg_base = NULL;
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return 1;
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}
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/***********/
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/***********/
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int mv643xx_eth_add_pds(void)
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{
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int ret = 0;
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static struct pci_device_id pci_marvell_mv64360[] = {
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@ -93,9 +176,38 @@ mv643xx_eth_add_pds(void)
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{ }
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};
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: init\n");
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#endif
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if (pci_dev_present(pci_marvell_mv64360)) {
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ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
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ret = platform_add_devices(mv643xx_eth_pd_devs,
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ARRAY_SIZE(mv643xx_eth_pd_devs));
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if ( Enable_SRAM() < 0)
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{
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eth0_pd.tx_sram_addr = 0;
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eth0_pd.tx_sram_size = 0;
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eth0_pd.rx_sram_addr = 0;
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eth0_pd.rx_sram_size = 0;
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eth1_pd.tx_sram_addr = 0;
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eth1_pd.tx_sram_size = 0;
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eth1_pd.rx_sram_addr = 0;
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eth1_pd.rx_sram_size = 0;
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: Can't enable the "
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"SRAM\n");
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#endif
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}
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}
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#ifdef BE_VERBOSE
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printk("Pegasos II/Marvell MV64361: init is over\n");
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#endif
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return ret;
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}
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device_initcall(mv643xx_eth_add_pds);
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