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Merge branch 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into v4.8/drivers
* 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: meson-gxbb: Export PWM related clocks for DT meson: clk: Add support for clock gates gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b clk: meson: Copy meson8b CLKID defines to private header file meson: clk: Rename register names according to Amlogic datasheet meson: clk: Move register definitions to meson8b.h clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe() clk: meson: Add GXBB AO Clock and Reset controller driver dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings clk: gxbb: add MMC gate clocks, and expose for DT
This commit is contained in:
Kevin Hilman
commit
dcdcc66022
@ -0,0 +1,45 @@
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* Amlogic GXBB AO Clock and Reset Unit
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The Amlogic GXBB AO clock controller generates and supplies clock to various
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controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-aoclkc"
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
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used in device tree sources.
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- #reset-cells: should be 1.
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Each reset is assigned an identifier and client nodes can use this identifier
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to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Example: AO Clock controller node:
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x040 0x0 0x4>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x4c0 0x14>;
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interrupts = <0 90 1>;
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clocks = <&clkc_AO CLKID_AO_UART1>;
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resets = <&clkc_AO RESET_AO_UART1>;
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status = "disabled";
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};
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@ -3,5 +3,5 @@
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#
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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@ -98,7 +98,7 @@ struct meson_clk_mpll {
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};
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#define MESON_GATE(_name, _reg, _bit) \
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struct clk_gate gxbb_##_name = { \
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struct clk_gate _name = { \
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.reg = (void __iomem *) _reg, \
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.bit_idx = (_bit), \
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.lock = &clk_lock, \
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191
drivers/clk/meson/gxbb-aoclk.c
Normal file
191
drivers/clk/meson/gxbb-aoclk.c
Normal file
@ -0,0 +1,191 @@
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/init.h>
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#include <dt-bindings/clock/gxbb-aoclkc.h>
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#include <dt-bindings/reset/gxbb-aoclkc.h>
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static DEFINE_SPINLOCK(gxbb_aoclk_lock);
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struct gxbb_aoclk_reset_controller {
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struct reset_controller_dev reset;
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unsigned int *data;
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void __iomem *base;
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};
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static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gxbb_aoclk_reset_controller *reset =
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container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
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writel(BIT(reset->data[id]), reset->base);
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return 0;
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}
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static const struct reset_control_ops gxbb_aoclk_reset_ops = {
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.reset = gxbb_aoclk_do_reset,
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};
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#define GXBB_AO_GATE(_name, _bit) \
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static struct clk_gate _name##_ao = { \
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.reg = (void __iomem *)0, \
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.bit_idx = (_bit), \
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.lock = &gxbb_aoclk_lock, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &clk_gate_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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}
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GXBB_AO_GATE(remote, 0);
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GXBB_AO_GATE(i2c_master, 1);
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GXBB_AO_GATE(i2c_slave, 2);
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GXBB_AO_GATE(uart1, 3);
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GXBB_AO_GATE(uart2, 5);
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GXBB_AO_GATE(ir_blaster, 6);
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static unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_REMOTE] = 16,
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[RESET_AO_I2C_MASTER] = 18,
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[RESET_AO_I2C_SLAVE] = 19,
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[RESET_AO_UART1] = 17,
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[RESET_AO_UART2] = 22,
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct clk_gate *gxbb_aoclk_gate[] = {
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[CLKID_AO_REMOTE] = &remote_ao,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
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[CLKID_AO_UART1] = &uart1_ao,
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[CLKID_AO_UART2] = &uart2_ao,
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[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
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};
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static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
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.hws = {
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[CLKID_AO_REMOTE] = &remote_ao.hw,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
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[CLKID_AO_UART1] = &uart1_ao.hw,
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[CLKID_AO_UART2] = &uart2_ao.hw,
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[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
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},
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.num = ARRAY_SIZE(gxbb_aoclk_gate),
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};
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static int gxbb_aoclkc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *base;
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int ret, clkid;
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struct device *dev = &pdev->dev;
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struct gxbb_aoclk_reset_controller *rstc;
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rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
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if (!rstc)
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return -ENOMEM;
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/* Generic clocks */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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/* Reset Controller */
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rstc->base = base;
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rstc->data = gxbb_aoclk_reset;
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rstc->reset.ops = &gxbb_aoclk_reset_ops;
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rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
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rstc->reset.of_node = dev->of_node;
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ret = devm_reset_controller_register(dev, &rstc->reset);
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/*
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* Populate base address and register all clks
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*/
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for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
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gxbb_aoclk_gate[clkid]->reg = base;
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ret = devm_clk_hw_register(dev,
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gxbb_aoclk_onecell_data.hws[clkid]);
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if (ret)
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return ret;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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&gxbb_aoclk_onecell_data);
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}
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static const struct of_device_id gxbb_aoclkc_match_table[] = {
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{ .compatible = "amlogic,gxbb-aoclkc" },
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{ }
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};
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static struct platform_driver gxbb_aoclkc_driver = {
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.probe = gxbb_aoclkc_probe,
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.driver = {
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.name = "gxbb-aoclkc",
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.of_match_table = gxbb_aoclkc_match_table,
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},
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};
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builtin_platform_driver(gxbb_aoclkc_driver);
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@ -565,90 +565,93 @@ static struct clk_gate gxbb_clk81 = {
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
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static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
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static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
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static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
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static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
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static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
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static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
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static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
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static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
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static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
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static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
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static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
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static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
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static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
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static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
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static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
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static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
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static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
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static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
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static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
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static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
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static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
|
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static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
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static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
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static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
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static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
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static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
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static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
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static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
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static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
|
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static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
|
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static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
|
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static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
|
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static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
|
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static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
|
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static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
|
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static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
|
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|
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static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
|
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static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
|
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static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
|
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static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
|
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static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
|
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static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
|
||||
static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
|
||||
static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
|
||||
static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
|
||||
static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
|
||||
static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
|
||||
static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
|
||||
static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
|
||||
static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
|
||||
static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
|
||||
static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
|
||||
static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
|
||||
static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
|
||||
static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
|
||||
static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
|
||||
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
|
||||
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
|
||||
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
|
||||
static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
|
||||
static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
|
||||
static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
|
||||
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
|
||||
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
|
||||
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
|
||||
static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
|
||||
static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
|
||||
static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
|
||||
static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
|
||||
static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
|
||||
static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
|
||||
static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
|
||||
static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
|
||||
static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
|
||||
static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
|
||||
static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
|
||||
|
||||
static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
|
||||
static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
|
||||
static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
|
||||
static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
|
||||
static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
|
||||
static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
|
||||
static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
|
||||
static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
|
||||
static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
|
||||
static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
|
||||
static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
|
||||
static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
|
||||
static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
|
||||
static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
|
||||
static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
|
||||
static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
|
||||
static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
|
||||
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
|
||||
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
|
||||
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
|
||||
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
|
||||
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
|
||||
|
||||
static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
|
||||
static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
|
||||
static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
|
||||
static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
|
||||
static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
|
||||
static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
|
||||
static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
|
||||
static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
|
||||
static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
|
||||
static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
|
||||
static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
|
||||
static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
|
||||
static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
|
||||
static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
|
||||
static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
|
||||
static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
|
||||
static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
|
||||
static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
|
||||
static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
|
||||
static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
|
||||
static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
|
||||
static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
|
||||
static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
|
||||
static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
|
||||
static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
|
||||
static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
|
||||
static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
|
||||
static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
|
||||
static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
|
||||
static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
|
||||
static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
|
||||
static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
|
||||
|
||||
/* Always On (AO) domain gates */
|
||||
|
||||
static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
|
||||
static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
|
||||
static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
|
||||
static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
|
||||
static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
|
||||
static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
|
||||
static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
|
||||
static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
|
||||
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
|
||||
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
|
||||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
||||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
|
||||
&gxbb_ao_ahb_bus,
|
||||
&gxbb_ao_iface,
|
||||
&gxbb_ao_i2c,
|
||||
&gxbb_emmc_a,
|
||||
&gxbb_emmc_b,
|
||||
&gxbb_emmc_c,
|
||||
};
|
||||
|
||||
static int gxbb_clkc_probe(struct platform_device *pdev)
|
||||
|
||||
@ -170,11 +170,11 @@
|
||||
*/
|
||||
#define CLKID_SYS_PLL 0
|
||||
/* CLKID_CPUCLK */
|
||||
#define CLKID_HDMI_PLL 2
|
||||
/* CLKID_HDMI_PLL */
|
||||
#define CLKID_FIXED_PLL 3
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
/* CLKID_FCLK_DIV3 */
|
||||
/* CLKID_FCLK_DIV4 */
|
||||
#define CLKID_FCLK_DIV5 7
|
||||
#define CLKID_FCLK_DIV7 8
|
||||
#define CLKID_GP0_PLL 9
|
||||
@ -262,8 +262,11 @@
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_AO_I2C 93
|
||||
/* CLKID_SD_EMMC_A */
|
||||
/* CLKID_SD_EMMC_B */
|
||||
/* CLKID_SD_EMMC_C */
|
||||
|
||||
#define NR_CLKS 94
|
||||
#define NR_CLKS 97
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
@ -23,27 +23,11 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/meson8b-clkc.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include "clkc.h"
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the HardKernel[0] data sheet are listed in comment
|
||||
* blocks below. Those offsets must be multiplied by 4 before adding them to
|
||||
* the base address to get the right value
|
||||
*
|
||||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
|
||||
#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
|
||||
#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
|
||||
#define MESON8B_REG_PLL_FIXED 0x0280
|
||||
#define MESON8B_REG_PLL_SYS 0x0300
|
||||
#define MESON8B_REG_PLL_VID 0x0320
|
||||
#include "meson8b.h"
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
@ -128,17 +112,17 @@ static struct clk_fixed_rate meson8b_xtal = {
|
||||
|
||||
static struct meson_clk_pll meson8b_fixed_pll = {
|
||||
.m = {
|
||||
.reg_off = MESON8B_REG_PLL_FIXED,
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = MESON8B_REG_PLL_FIXED,
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = MESON8B_REG_PLL_FIXED,
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
@ -154,17 +138,17 @@ static struct meson_clk_pll meson8b_fixed_pll = {
|
||||
|
||||
static struct meson_clk_pll meson8b_vid_pll = {
|
||||
.m = {
|
||||
.reg_off = MESON8B_REG_PLL_VID,
|
||||
.reg_off = HHI_VID_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = MESON8B_REG_PLL_VID,
|
||||
.reg_off = HHI_VID_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = MESON8B_REG_PLL_VID,
|
||||
.reg_off = HHI_VID_PLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
@ -180,17 +164,17 @@ static struct meson_clk_pll meson8b_vid_pll = {
|
||||
|
||||
static struct meson_clk_pll meson8b_sys_pll = {
|
||||
.m = {
|
||||
.reg_off = MESON8B_REG_PLL_SYS,
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = MESON8B_REG_PLL_SYS,
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = MESON8B_REG_PLL_SYS,
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
@ -267,7 +251,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
|
||||
* forthcoming coordinated clock rates feature
|
||||
*/
|
||||
static struct meson_clk_cpu meson8b_cpu_clk = {
|
||||
.reg_off = MESON8B_REG_SYS_CPU_CNTL1,
|
||||
.reg_off = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.div_table = cpu_div_table,
|
||||
.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
@ -281,7 +265,7 @@ static struct meson_clk_cpu meson8b_cpu_clk = {
|
||||
static u32 mux_table_clk81[] = { 6, 5, 7 };
|
||||
|
||||
struct clk_mux meson8b_mpeg_clk_sel = {
|
||||
.reg = (void *)MESON8B_REG_HHI_MPEG,
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 12,
|
||||
.flags = CLK_MUX_READ_ONLY,
|
||||
@ -303,7 +287,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
|
||||
};
|
||||
|
||||
struct clk_divider meson8b_mpeg_clk_div = {
|
||||
.reg = (void *)MESON8B_REG_HHI_MPEG,
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
@ -317,7 +301,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
|
||||
};
|
||||
|
||||
struct clk_gate meson8b_clk81 = {
|
||||
.reg = (void *)MESON8B_REG_HHI_MPEG,
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
@ -329,6 +313,92 @@ struct clk_gate meson8b_clk81 = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
|
||||
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
|
||||
static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
|
||||
static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
|
||||
static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
|
||||
static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
|
||||
static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
|
||||
static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
|
||||
static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
|
||||
static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
|
||||
static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
|
||||
static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
|
||||
static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
|
||||
static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
|
||||
static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
|
||||
static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
|
||||
static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
|
||||
static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
|
||||
static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
|
||||
|
||||
static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
|
||||
static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
|
||||
static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
|
||||
static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
|
||||
static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
|
||||
static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
|
||||
static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
|
||||
static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
|
||||
static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
|
||||
static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
|
||||
static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
|
||||
static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
|
||||
static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
|
||||
static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
|
||||
static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
|
||||
static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
|
||||
static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
|
||||
static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
|
||||
static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
|
||||
static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
|
||||
|
||||
static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
|
||||
static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
|
||||
static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
|
||||
static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
|
||||
static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
|
||||
static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
|
||||
static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
|
||||
static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
|
||||
static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
|
||||
static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
|
||||
static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
|
||||
|
||||
static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
|
||||
static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
|
||||
static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
|
||||
static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
|
||||
static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
|
||||
static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
|
||||
static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
|
||||
static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
|
||||
static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
|
||||
static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
|
||||
static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
|
||||
static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
|
||||
static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
|
||||
static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
|
||||
static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
|
||||
static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
|
||||
|
||||
/* Always On (AO) domain gates */
|
||||
|
||||
static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
|
||||
static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
|
||||
static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
|
||||
static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
|
||||
|
||||
static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
||||
@ -344,6 +414,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &meson8b_clk81.hw,
|
||||
[CLKID_DDR] = &meson8b_ddr.hw,
|
||||
[CLKID_DOS] = &meson8b_dos.hw,
|
||||
[CLKID_ISA] = &meson8b_isa.hw,
|
||||
[CLKID_PL301] = &meson8b_pl301.hw,
|
||||
[CLKID_PERIPHS] = &meson8b_periphs.hw,
|
||||
[CLKID_SPICC] = &meson8b_spicc.hw,
|
||||
[CLKID_I2C] = &meson8b_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &meson8b_smart_card.hw,
|
||||
[CLKID_RNG0] = &meson8b_rng0.hw,
|
||||
[CLKID_UART0] = &meson8b_uart0.hw,
|
||||
[CLKID_SDHC] = &meson8b_sdhc.hw,
|
||||
[CLKID_STREAM] = &meson8b_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
|
||||
[CLKID_SDIO] = &meson8b_sdio.hw,
|
||||
[CLKID_ABUF] = &meson8b_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
|
||||
[CLKID_SPI] = &meson8b_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &meson8b_eth.hw,
|
||||
[CLKID_DEMUX] = &meson8b_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &meson8b_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &meson8b_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &meson8b_aififo2.hw,
|
||||
[CLKID_MIXER] = &meson8b_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
|
||||
[CLKID_ADC] = &meson8b_adc.hw,
|
||||
[CLKID_BLKMV] = &meson8b_blkmv.hw,
|
||||
[CLKID_AIU] = &meson8b_aiu.hw,
|
||||
[CLKID_UART1] = &meson8b_uart1.hw,
|
||||
[CLKID_G2D] = &meson8b_g2d.hw,
|
||||
[CLKID_USB0] = &meson8b_usb0.hw,
|
||||
[CLKID_USB1] = &meson8b_usb1.hw,
|
||||
[CLKID_RESET] = &meson8b_reset.hw,
|
||||
[CLKID_NAND] = &meson8b_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
|
||||
[CLKID_USB] = &meson8b_usb.hw,
|
||||
[CLKID_VDIN1] = &meson8b_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &meson8b_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &meson8b_dvin.hw,
|
||||
[CLKID_UART2] = &meson8b_uart2.hw,
|
||||
[CLKID_SANA] = &meson8b_sana.hw,
|
||||
[CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &meson8b_enc480p.hw,
|
||||
[CLKID_RNG1] = &meson8b_rng1.hw,
|
||||
[CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
|
||||
[CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
|
||||
[CLKID_EDP] = &meson8b_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
};
|
||||
@ -354,6 +501,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
|
||||
&meson8b_sys_pll,
|
||||
};
|
||||
|
||||
static struct clk_gate *meson8b_clk_gates[] = {
|
||||
&meson8b_clk81,
|
||||
&meson8b_ddr,
|
||||
&meson8b_dos,
|
||||
&meson8b_isa,
|
||||
&meson8b_pl301,
|
||||
&meson8b_periphs,
|
||||
&meson8b_spicc,
|
||||
&meson8b_i2c,
|
||||
&meson8b_sar_adc,
|
||||
&meson8b_smart_card,
|
||||
&meson8b_rng0,
|
||||
&meson8b_uart0,
|
||||
&meson8b_sdhc,
|
||||
&meson8b_stream,
|
||||
&meson8b_async_fifo,
|
||||
&meson8b_sdio,
|
||||
&meson8b_abuf,
|
||||
&meson8b_hiu_iface,
|
||||
&meson8b_assist_misc,
|
||||
&meson8b_spi,
|
||||
&meson8b_i2s_spdif,
|
||||
&meson8b_eth,
|
||||
&meson8b_demux,
|
||||
&meson8b_aiu_glue,
|
||||
&meson8b_iec958,
|
||||
&meson8b_i2s_out,
|
||||
&meson8b_amclk,
|
||||
&meson8b_aififo2,
|
||||
&meson8b_mixer,
|
||||
&meson8b_mixer_iface,
|
||||
&meson8b_adc,
|
||||
&meson8b_blkmv,
|
||||
&meson8b_aiu,
|
||||
&meson8b_uart1,
|
||||
&meson8b_g2d,
|
||||
&meson8b_usb0,
|
||||
&meson8b_usb1,
|
||||
&meson8b_reset,
|
||||
&meson8b_nand,
|
||||
&meson8b_dos_parser,
|
||||
&meson8b_usb,
|
||||
&meson8b_vdin1,
|
||||
&meson8b_ahb_arb0,
|
||||
&meson8b_efuse,
|
||||
&meson8b_boot_rom,
|
||||
&meson8b_ahb_data_bus,
|
||||
&meson8b_ahb_ctrl_bus,
|
||||
&meson8b_hdmi_intr_sync,
|
||||
&meson8b_hdmi_pclk,
|
||||
&meson8b_usb1_ddr_bridge,
|
||||
&meson8b_usb0_ddr_bridge,
|
||||
&meson8b_mmc_pclk,
|
||||
&meson8b_dvin,
|
||||
&meson8b_uart2,
|
||||
&meson8b_sana,
|
||||
&meson8b_vpu_intr,
|
||||
&meson8b_sec_ahb_ahb3_bridge,
|
||||
&meson8b_clk81_a9,
|
||||
&meson8b_vclk2_venci0,
|
||||
&meson8b_vclk2_venci1,
|
||||
&meson8b_vclk2_vencp0,
|
||||
&meson8b_vclk2_vencp1,
|
||||
&meson8b_gclk_venci_int,
|
||||
&meson8b_gclk_vencp_int,
|
||||
&meson8b_dac_clk,
|
||||
&meson8b_aoclk_gate,
|
||||
&meson8b_iec958_gate,
|
||||
&meson8b_enc480p,
|
||||
&meson8b_rng1,
|
||||
&meson8b_gclk_vencl_int,
|
||||
&meson8b_vclk2_venclmcc,
|
||||
&meson8b_vclk2_vencl,
|
||||
&meson8b_vclk2_other,
|
||||
&meson8b_edp,
|
||||
&meson8b_ao_media_cpu,
|
||||
&meson8b_ao_ahb_sram,
|
||||
&meson8b_ao_ahb_bus,
|
||||
&meson8b_ao_iface,
|
||||
};
|
||||
|
||||
static int meson8b_clkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *clk_base;
|
||||
@ -381,6 +609,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
|
||||
meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
|
||||
meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
|
||||
meson8b_clk_gates[i]->reg = clk_base +
|
||||
(u32)meson8b_clk_gates[i]->reg;
|
||||
|
||||
/*
|
||||
* register all clks
|
||||
* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
|
||||
151
drivers/clk/meson/meson8b.h
Normal file
151
drivers/clk/meson/meson8b.h
Normal file
@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Endless Mobile, Inc.
|
||||
* Author: Carlo Caione <carlo@endlessm.com>
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, Inc.
|
||||
* Michael Turquette <mturquette@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __MESON8B_H
|
||||
#define __MESON8B_H
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the HardKernel[0] data sheet are listed in comment
|
||||
* blocks below. Those offsets must be multiplied by 4 before adding them to
|
||||
* the base address to get the right value
|
||||
*
|
||||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
|
||||
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
|
||||
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
|
||||
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
|
||||
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
|
||||
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* Migrate them out of this header and into the DT header file when they need
|
||||
* to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
|
||||
*/
|
||||
|
||||
/* CLKID_UNUSED */
|
||||
/* CLKID_XTAL */
|
||||
/* CLKID_PLL_FIXED */
|
||||
/* CLKID_PLL_VID */
|
||||
/* CLKID_PLL_SYS */
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
/* CLKID_FCLK_DIV3 */
|
||||
/* CLKID_FCLK_DIV4 */
|
||||
/* CLKID_FCLK_DIV5 */
|
||||
/* CLKID_FCLK_DIV7 */
|
||||
/* CLKID_CLK81 */
|
||||
/* CLKID_MALI */
|
||||
/* CLKID_CPUCLK */
|
||||
/* CLKID_ZERO */
|
||||
/* CLKID_MPEG_SEL */
|
||||
/* CLKID_MPEG_DIV */
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A9 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT 77
|
||||
#define CLKID_GCLK_VENCP_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCL_INT 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK2_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
|
||||
#define CLK_NR_CLKS 93
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/meson8b-clkc.h>
|
||||
|
||||
#endif /* __MESON8B_H */
|
||||
66
include/dt-bindings/clock/gxbb-aoclkc.h
Normal file
66
include/dt-bindings/clock/gxbb-aoclkc.h
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
|
||||
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
|
||||
|
||||
#define CLKID_AO_REMOTE 0
|
||||
#define CLKID_AO_I2C_MASTER 1
|
||||
#define CLKID_AO_I2C_SLAVE 2
|
||||
#define CLKID_AO_UART1 3
|
||||
#define CLKID_AO_UART2 4
|
||||
#define CLKID_AO_IR_BLASTER 5
|
||||
|
||||
#endif
|
||||
@ -6,7 +6,14 @@
|
||||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_CPUCLK 1
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
#define CLKID_SD_EMMC_C 96
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
||||
@ -22,6 +22,4 @@
|
||||
#define CLKID_MPEG_SEL 14
|
||||
#define CLKID_MPEG_DIV 15
|
||||
|
||||
#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1)
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
||||
66
include/dt-bindings/reset/gxbb-aoclkc.h
Normal file
66
include/dt-bindings/reset/gxbb-aoclkc.h
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
|
||||
|
||||
#define RESET_AO_REMOTE 0
|
||||
#define RESET_AO_I2C_MASTER 1
|
||||
#define RESET_AO_I2C_SLAVE 2
|
||||
#define RESET_AO_UART1 3
|
||||
#define RESET_AO_UART2 4
|
||||
#define RESET_AO_IR_BLASTER 5
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user