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MediaTek ARM64 DeviceTree updates for v6.13

Browse Source 
MT8195 (also called MT8395)
  - Enabled GPU support on Genio 1200 EVK
  - Added sound-dai-cells for audio codec on MT8195 Cherry Chromebooks
 
 MT8192:
  - Added support Asurada Chromebook variants with Synaptics trackpad
 
 MT8188 (also called MT8390):
  - Added support for CPU DVFS, IOMMU, PWM hardware, SPMI bus,
    Audio, socinfo, PCI-Express, DisplayPort, MIPI DSI, Ethernet,
    Video HW Encoders (Stateful) and HW Decoders (Stateless),
    JPEG HW Encoder/Decoder.
  - Enabled GPU support on Genio 700 EVK
 
 MT8183:
  - Added support for Video HW Encoders (Stateful)
  - Added HDMI support on MT8183 Pumpkin board
  - Fixed some regulators to provide the actual description of the
    power rails in MT8183 Kukui Chromebooks
  - Disabled DPI display interface on MT8183 Kukui Chromebooks
    to fix internal display probing
  - Fixed address of EEPROM found on MT8183 Kakadu/Kodama Chromebooks
  - Added SCL internal delay on I2C2 bus for improved I2C-HID devices
    reliability on MT8183 Jacuzzi Chromebooks
 
 MT7988:
  - Added support for eFuses and UART controllers
 
 Plus, addition of OF Graph support in MediaTek MMSYS and some cleanups
 and dtbs_check fixes for MT8195 and for all machines using the MT6358
 PMIC.
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Merge tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

MediaTek ARM64 DeviceTree updates for v6.13

MT8195 (also called MT8395)
 - Enabled GPU support on Genio 1200 EVK
 - Added sound-dai-cells for audio codec on MT8195 Cherry Chromebooks

MT8192:
 - Added support Asurada Chromebook variants with Synaptics trackpad

MT8188 (also called MT8390):
 - Added support for CPU DVFS, IOMMU, PWM hardware, SPMI bus,
   Audio, socinfo, PCI-Express, DisplayPort, MIPI DSI, Ethernet,
   Video HW Encoders (Stateful) and HW Decoders (Stateless),
   JPEG HW Encoder/Decoder.
 - Enabled GPU support on Genio 700 EVK

MT8183:
 - Added support for Video HW Encoders (Stateful)
 - Added HDMI support on MT8183 Pumpkin board
 - Fixed some regulators to provide the actual description of the
   power rails in MT8183 Kukui Chromebooks
 - Disabled DPI display interface on MT8183 Kukui Chromebooks
   to fix internal display probing
 - Fixed address of EEPROM found on MT8183 Kakadu/Kodama Chromebooks
 - Added SCL internal delay on I2C2 bus for improved I2C-HID devices
   reliability on MT8183 Jacuzzi Chromebooks

MT7988:
 - Added support for eFuses and UART controllers

Plus, addition of OF Graph support in MediaTek MMSYS and some cleanups
and dtbs_check fixes for MT8195 and for all machines using the MT6358
PMIC.

* tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (55 commits)
  arm64: dts: mediatek: mt8183-kukui: Drop bogus fixed regulators
  arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed regulators
  arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names
  arm64: dts: mediatek: mt6358: fix dtbs_check error
  arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity
  arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns
  arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns
  arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns
  arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns
  dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
  arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread
  arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI
  arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status
  arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source trackpad
  arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes
  arm64: dts: mediatek: mt8390-genio-700-evk: Enable ethernet
  arm64: dts: mediatek: mt8188: Add ethernet node
  arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes
  arm64: dts: mediatek: mt8188: Add DP-INTF nodes
  arm64: dts: mediatek: mt8188: Add display nodes for vdosys1
  ...

Link: https://lore.kernel.org/r/20241104112625.161365-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-11-12 22:41:15 +01:00
commit dc2fe29c88
28 changed files with 1586 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -93,6 +93,34 @@ properties:
'#reset-cells':
const: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port connects the MMSYS/VDOSYS output to
the first component of one display pipeline, for example one of
the available OVL or RDMA blocks.
Some MediaTek SoCs support multiple display outputs per MMSYS.
properties:
endpoint@0:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the primary display pipeline
endpoint@1:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the secondary display pipeline
endpoint@2:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the tertiary display pipeline
anyOf:
- required:
- endpoint@0
- required:
- endpoint@1
- required:
- endpoint@2
required:
- compatible
- reg

4
arch/arm64/boot/dts/mediatek/mt6358.dtsi
View File

@ -15,12 +15,12 @@
#io-channel-cells = <1>;
};
mt6358codec: mt6358codec {
mt6358codec: audio-codec {
compatible = "mediatek,mt6358-sound";
mediatek,dmic-mode = <0>; /* two-wires */
};
mt6358regulator: mt6358regulator {
mt6358regulator: regulators {
compatible = "mediatek,mt6358-regulator";
mt6358_vdram1_reg: buck_vdram1 {

42
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -86,7 +86,7 @@
#clock-cells = <1>;
};
clock-controller@1001b000 {
topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7988-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
@ -124,6 +124,39 @@
status = "disabled";
};
serial@11000000 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART0_CK>;
clock-names = "baud", "bus";
status = "disabled";
};
serial@11000100 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART1_CK>;
clock-names = "baud", "bus";
status = "disabled";
};
serial@11000200 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART2_CK>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
@ -198,6 +231,13 @@
#clock-cells = <1>;
};
efuse@11f50000 {
compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
reg = <0 0x11f50000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
clock-controller@15000000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;

8
arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi
View File

@ -49,6 +49,14 @@
interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
reg = <0x2c>;
hid-descr-addr = <0x0020>;
/*
* The trackpad needs a post-power-on delay of 100ms,
* but at time of writing, the power supply for it on
* this board is always on. The delay is therefore not
* added to avoid impacting the readiness of the
* trackpad.
*/
vdd-supply = <&mt6397_vgp6_reg>;
wakeup-source;
};
};

3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
View File

@ -30,3 +30,6 @@
};
};
&i2c2 {
i2c-scl-internal-delay-ns = <4100>;
};

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
View File

@ -18,6 +18,8 @@
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;

3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View File

@ -30,3 +30,6 @@
qcom,ath10k-calibration-variant = "GO_DAMU";
};
&i2c2 {
i2c-scl-internal-delay-ns = <20000>;
};

3
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
View File

@ -25,3 +25,6 @@
};
};
&i2c2 {
i2c-scl-internal-delay-ns = <21500>;
};

30
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@ -8,28 +8,32 @@
#include <arm/cros-ec-keyboard.dtsi>
/ {
pp1200_mipibrdg: pp1200-mipibrdg {
pp1000_mipibrdg: pp1000-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "pp1200_mipibrdg";
regulator-name = "pp1000_mipibrdg";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pp1200_mipibrdg_en>;
pinctrl-0 = <&pp1000_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 54 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp1800_alw>;
};
pp1800_mipibrdg: pp1800-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "pp1800_mipibrdg";
pinctrl-names = "default";
pinctrl-0 = <&pp1800_lcd_en>;
pinctrl-0 = <&pp1800_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp1800_alw>;
};
pp3300_panel: pp3300-panel {
@ -44,18 +48,20 @@
regulator-boot-on;
gpio = <&pio 35 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_alw>;
};
vddio_mipibrdg: vddio-mipibrdg {
pp3300_mipibrdg: pp3300-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "vddio_mipibrdg";
regulator-name = "pp3300_mipibrdg";
pinctrl-names = "default";
pinctrl-0 = <&vddio_mipibrdg_en>;
pinctrl-0 = <&pp3300_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 37 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_alw>;
};
volume_buttons: volume-buttons {
@ -146,9 +152,9 @@
pinctrl-0 = <&anx7625_pins>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1200_mipibrdg>;
vdd10-supply = <&pp1000_mipibrdg>;
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&vddio_mipibrdg>;
vdd33-supply = <&pp3300_mipibrdg>;
ports {
#address-cells = <1>;
@ -391,14 +397,14 @@
"",
"";
pp1200_mipibrdg_en: pp1200-mipibrdg-en {
pp1000_mipibrdg_en: pp1000-mipibrdg-en {
pins1 {
pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
output-low;
};
};
pp1800_lcd_en: pp1800-lcd-en {
pp1800_mipibrdg_en: pp1800-mipibrdg-en {
pins1 {
pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
output-low;
@ -460,7 +466,7 @@
};
};
vddio_mipibrdg_en: vddio-mipibrdg-en {
pp3300_mipibrdg_en: pp3300-mipibrdg-en {
pins1 {
pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
output-low;

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
View File

@ -92,9 +92,9 @@
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x54>;
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
View File

@ -23,7 +23,7 @@
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
vdd-supply = <&lcd_pp3300>;
vdd-supply = <&pp3300_alw>;
};
};

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
View File

@ -23,7 +23,7 @@
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
vdd-supply = <&lcd_pp3300>;
vdd-supply = <&pp3300_alw>;
};
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
View File

@ -79,9 +79,9 @@
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x54>;
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
View File

@ -88,9 +88,9 @@
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x54>;
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};

30
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -52,27 +52,6 @@
vin-supply = <&pp1800_alw>;
};
lcd_pp3300: regulator1 {
compatible = "regulator-fixed";
regulator-name = "lcd_pp3300";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
mmc1_fixed_power: regulator3 {
compatible = "regulator-fixed";
regulator-name = "mmc1_power";
vin-supply = <&pp3300_alw>;
};
mmc1_fixed_io: regulator4 {
compatible = "regulator-fixed";
regulator-name = "mmc1_io";
vin-supply = <&pp1800_alw>;
};
pp1800_alw: regulator5 {
compatible = "regulator-fixed";
regulator-name = "pp1800_alw";
@ -290,6 +269,11 @@
};
};
&dpi0 {
/* TODO Re-enable after DP to Type-C port muxing can be described */
status = "disabled";
};
&gic {
mediatek,broken-save-restore-fw;
};
@ -369,8 +353,8 @@
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
vmmc-supply = <&mmc1_fixed_power>;
vqmmc-supply = <&mmc1_fixed_io>;
vmmc-supply = <&pp3300_alw>;
vqmmc-supply = <&pp1800_alw>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
max-frequency = <200000000>;

123
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@ -63,6 +63,18 @@
pulldown-ohm = <0>;
io-channels = <&auxadc 0>;
};
connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "d";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_connector_out>;
};
};
};
};
&auxadc {
@ -120,6 +132,43 @@
pinctrl-0 = <&i2c6_pins>;
status = "okay";
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
it66121hdmitx: hdmitx@4c {
compatible = "ite,it66121";
reg = <0x4c>;
pinctrl-names = "default";
pinctrl-0 = <&ite_pins>;
reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>;
interrupt-parent = <&pio>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
vcn33-supply = <&mt6358_vcn33_reg>;
vcn18-supply = <&mt6358_vcn18_reg>;
vrf12-supply = <&mt6358_vrf12_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
it66121_in: endpoint {
bus-width = <12>;
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
hdmi_connector_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&keyboard {
@ -362,6 +411,67 @@
input-enable;
};
};
ite_pins: ite-pins {
pins-irq {
pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
input-enable;
bias-pull-up;
};
pins-rst {
pinmux = <PINMUX_GPIO160__FUNC_GPIO160>;
output-high;
};
};
dpi_func_pins: dpi-func-pins {
pins-dpi {
pinmux = <PINMUX_GPIO12__FUNC_I2S5_BCK>,
<PINMUX_GPIO46__FUNC_I2S5_LRCK>,
<PINMUX_GPIO47__FUNC_I2S5_DO>,
<PINMUX_GPIO13__FUNC_DBPI_D0>,
<PINMUX_GPIO14__FUNC_DBPI_D1>,
<PINMUX_GPIO15__FUNC_DBPI_D2>,
<PINMUX_GPIO16__FUNC_DBPI_D3>,
<PINMUX_GPIO17__FUNC_DBPI_D4>,
<PINMUX_GPIO18__FUNC_DBPI_D5>,
<PINMUX_GPIO19__FUNC_DBPI_D6>,
<PINMUX_GPIO20__FUNC_DBPI_D7>,
<PINMUX_GPIO21__FUNC_DBPI_D8>,
<PINMUX_GPIO22__FUNC_DBPI_D9>,
<PINMUX_GPIO23__FUNC_DBPI_D10>,
<PINMUX_GPIO24__FUNC_DBPI_D11>,
<PINMUX_GPIO25__FUNC_DBPI_HSYNC>,
<PINMUX_GPIO26__FUNC_DBPI_VSYNC>,
<PINMUX_GPIO27__FUNC_DBPI_DE>,
<PINMUX_GPIO28__FUNC_DBPI_CK>;
};
};
dpi_idle_pins: dpi-idle-pins {
pins-idle {
pinmux = <PINMUX_GPIO12__FUNC_GPIO12>,
<PINMUX_GPIO46__FUNC_GPIO46>,
<PINMUX_GPIO47__FUNC_GPIO47>,
<PINMUX_GPIO13__FUNC_GPIO13>,
<PINMUX_GPIO14__FUNC_GPIO14>,
<PINMUX_GPIO15__FUNC_GPIO15>,
<PINMUX_GPIO16__FUNC_GPIO16>,
<PINMUX_GPIO17__FUNC_GPIO17>,
<PINMUX_GPIO18__FUNC_GPIO18>,
<PINMUX_GPIO19__FUNC_GPIO19>,
<PINMUX_GPIO20__FUNC_GPIO20>,
<PINMUX_GPIO21__FUNC_GPIO21>,
<PINMUX_GPIO22__FUNC_GPIO22>,
<PINMUX_GPIO23__FUNC_GPIO23>,
<PINMUX_GPIO24__FUNC_GPIO24>,
<PINMUX_GPIO25__FUNC_GPIO25>,
<PINMUX_GPIO26__FUNC_GPIO26>,
<PINMUX_GPIO27__FUNC_GPIO27>,
<PINMUX_GPIO28__FUNC_GPIO28>;
};
};
};
&pmic {
@ -415,3 +525,16 @@
&dsi0 {
status = "disabled";
};
&dpi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dpi_func_pins>;
pinctrl-1 = <&dpi_idle_pins>;
status = "okay";
port {
dpi_out: endpoint {
remote-endpoint = <&it66121_in>;
};
};
};

21
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1845,6 +1845,10 @@
<&mmsys CLK_MM_DPI_MM>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
port {
dpi_out: endpoint { };
};
};
mutex: mutex@14016000 {
@ -1974,6 +1978,23 @@
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
};
vcodec_enc: vcodec@17020000 {
compatible = "mediatek,mt8183-vcodec-enc";
reg = <0 0x17020000 0 0x1000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
<&iommu M4U_PORT_VENC_RD_COMV>,
<&iommu M4U_PORT_VENC_CUR_LUMA>,
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>;
mediatek,scp = <&scp>;
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_VENC>;
clock-names = "venc_sel";
};
venc_jpg: jpeg-encoder@17030000 {
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;

21
arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi
View File

@ -10,12 +10,6 @@
/ {
chassis-type = "laptop";
max98360a: max98360a {
compatible = "maxim,max98360a";
sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&cpu6 {
@ -59,19 +53,14 @@
opp-hz = /bits/ 64 <2200000000>;
};
&rt1019p{
status = "disabled";
};
&sound {
compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound";
status = "okay";
};
spk-hdmi-playback-dai-link {
codec {
sound-dai = <&it6505dptx>, <&max98360a>;
};
};
&speaker_codec {
compatible = "maxim,max98360a";
sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
/delete-property/ sdb-gpios;
};
&spmi {

14
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
View File

@ -259,15 +259,15 @@
mediatek,clk-provider = "cpu";
/* RT1019P and IT6505 connected to the same I2S line */
codec {
sound-dai = <&it6505dptx>, <&rt1019p>;
sound-dai = <&it6505dptx>, <&speaker_codec>;
};
};
};
rt1019p: speaker-codec {
speaker_codec: speaker-codec {
compatible = "realtek,rt1019p";
pinctrl-names = "default";
pinctrl-0 = <&rt1019p_pins_default>;
pinctrl-0 = <&speaker_codec_pins_default>;
#sound-dai-cells = <0>;
sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
};
@ -423,7 +423,7 @@
#sound-dai-cells = <0>;
ovdd-supply = <&mt6366_vsim2_reg>;
pwr18-supply = <&pp1800_dpbrdg_dx>;
reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
@ -1179,7 +1179,7 @@
};
};
rt1019p_pins_default: rt1019p-default-pins {
speaker_codec_pins_default: speaker-codec-default-pins {
pins-sdb {
pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
output-low;
@ -1336,7 +1336,7 @@
regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
MT6397_BUCK_MODE_FORCE_PWM>;
regulator-coupled-with = <&mt6366_vsram_gpu_reg>;
regulator-coupled-max-spread = <10000>;
regulator-coupled-max-spread = <100000>;
};
mt6366_vproc11_reg: vproc11 {
@ -1545,7 +1545,7 @@
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <240>;
regulator-coupled-with = <&mt6366_vgpu_reg>;
regulator-coupled-max-spread = <10000>;
regulator-coupled-max-spread = <100000>;
};
mt6366_vsram_others_reg: vsram-others {

7
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -29,6 +29,13 @@
rdma1 = &rdma1;
};
fhctl: fhctl@1000ce00 {
compatible = "mediatek,mt8186-fhctl";
clocks = <&apmixedsys CLK_APMIXED_TVDPLL>;
reg = <0 0x1000ce00 0 0x200>;
status = "disabled";
};
cci: cci {
compatible = "mediatek,mt8186-cci";
clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,

2
arch/arm64/boot/dts/mediatek/mt8188-evb.dts
View File

@ -140,8 +140,6 @@
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&nor_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {

1124
arch/arm64/boot/dts/mediatek/mt8188.dtsi
View File

File diff suppressed because it is too large Load Diff

11
arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
View File

@ -79,3 +79,14 @@
&touchscreen {
compatible = "elan,ekth3500";
};
&i2c2 {
/* synaptics touchpad */
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};

4
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@ -335,14 +335,12 @@
clock-frequency = <400000>;
clock-stretch-ns = <12600>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
pinctrl-0 = <&i2c2_pins>, <&trackpad_pins>;
trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
vcc-supply = <&pp3300_u>;
wakeup-source;
};

6
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -438,7 +438,7 @@
/* Realtek RT5682i or RT5682s, sharing the same configuration */
reg = <0x1a>;
interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
realtek,jd-src = <1>;
AVDD-supply = <&mt6359_vio18_ldo_reg>;
@ -1181,7 +1181,7 @@
link-name = "ETDM1_OUT_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&audio_codec>;
sound-dai = <&audio_codec 0>;
};
};
@ -1189,7 +1189,7 @@
link-name = "ETDM2_IN_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&audio_codec>;
sound-dai = <&audio_codec 0>;
};
};

4
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -487,7 +487,7 @@
};
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
compatible = "mediatek,mt8195-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -3331,11 +3331,9 @@
mutex1: mutex@1c101000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c101000 0 0x1000>;
reg-names = "vdo1_mutex";
interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
clock-names = "vdo1_mutex";
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
};

192
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
View File

@ -23,6 +23,16 @@
"mediatek,mt8188";
aliases {
ethernet0 = &eth;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
mmc0 = &mmc0;
mmc1 = &mmc1;
serial0 = &uart0;
};
@ -87,109 +97,124 @@
common_fixed_5v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "5v_en";
regulator-name = "vdd_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_vsys>;
};
edp_panel_fixed_3v3: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "edp_panel_3v3";
regulator-name = "vedp_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&edp_panel_3v3_en_pins>;
vin-supply = <&reg_vsys>;
};
gpio_fixed_3v3: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "gpio_3v3_en";
regulator-name = "ext_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_vsys>;
};
/* system wide 4.2V power rail from charger */
reg_vsys: regulator-vsys {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-always-on;
regulator-boot-on;
};
/* used by mmc2 */
sdio_fixed_1v8: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "sdio_io";
regulator-name = "vio18_conn";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
regulator-always-on;
};
/* used by mmc2 */
sdio_fixed_3v3: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "sdio_card";
regulator-name = "wifi_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 74 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_vsys>;
};
touch0_fixed_3v3: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "touch_3v3";
regulator-name = "vio33_tp1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 119 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vsys>;
};
usb_hub_fixed_3v3: regulator-6 {
compatible = "regulator-fixed";
regulator-name = "usb_hub_3v3";
regulator-name = "vhub_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */
startup-delay-us = <10000>;
enable-active-high;
vin-supply = <&reg_vsys>;
};
usb_hub_reset_1v8: regulator-7 {
usb_p0_vbus: regulator-7 {
compatible = "regulator-fixed";
regulator-name = "usb_hub_reset";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */
vin-supply = <&usb_hub_fixed_3v3>;
};
usb_p0_vbus: regulator-8 {
compatible = "regulator-fixed";
regulator-name = "usb_p0_vbus";
regulator-name = "vbus_p0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 84 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vsys>;
};
usb_p1_vbus: regulator-9 {
usb_p1_vbus: regulator-8 {
compatible = "regulator-fixed";
regulator-name = "usb_p1_vbus";
regulator-name = "vbus_p1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 87 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vsys>;
};
usb_p2_vbus: regulator-10 {
/* used by ssusb2 */
usb_p2_vbus: regulator-9 {
compatible = "regulator-fixed";
regulator-name = "usb_p2_vbus";
regulator-name = "wifi_3v3";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
};
&gpu {
mali-supply = <&mt6359_vproc2_buck_reg>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@ -234,7 +259,6 @@
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
pinctrl-1 = <&rt1715_int_pins>;
clock-frequency = <1000000>;
status = "okay";
};
@ -253,6 +277,14 @@
status = "okay";
};
&mfg0 {
domain-supply = <&mt6359_vproc2_buck_reg>;
};
&mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
@ -295,38 +327,65 @@
};
&mt6359_vcn18_ldo_reg {
regulator-name = "vcn18_pmu";
regulator-always-on;
};
&mt6359_vcn33_2_bt_ldo_reg {
regulator-name = "vcn33_2_pmu";
regulator-always-on;
};
&mt6359_vcore_buck_reg {
regulator-name = "dvdd_proc_l";
regulator-always-on;
};
&mt6359_vgpu11_buck_reg {
regulator-name = "dvdd_core";
regulator-always-on;
};
&mt6359_vpa_buck_reg {
regulator-name = "vpa_pmu";
regulator-max-microvolt = <3100000>;
};
&mt6359_vproc2_buck_reg {
/* The name "vgpu" is required by mtk-regulator-coupler */
regulator-name = "vgpu";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <800000>;
regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
regulator-coupled-max-spread = <6250>;
};
&mt6359_vpu_buck_reg {
regulator-name = "dvdd_adsp";
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-name = "va12_abb2_pmu";
regulator-always-on;
};
&mt6359_vsim1_ldo_reg {
regulator-name = "vsim1_pmu";
regulator-enable-ramp-delay = <480>;
};
&mt6359_vsram_others_ldo_reg {
/* The name "vsram_gpu" is required by mtk-regulator-coupler */
regulator-name = "vsram_gpu";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
regulator-coupled-max-spread = <6250>;
};
&mt6359_vufs_ldo_reg {
regulator-name = "vufs18_pmu";
regulator-always-on;
};
@ -335,6 +394,16 @@
mediatek,mic-type-1 = <3>; /* DCC */
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins_default>;
status = "okay";
};
&pciephy {
status = "okay";
};
&pio {
audio_default_pins: audio-default-pins {
pins-cmd-dat {
@ -700,6 +769,15 @@
};
};
pcie_pins_default: pcie-default {
mux {
pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
<PINMUX_GPIO48__FUNC_O_PERSTN>,
<PINMUX_GPIO49__FUNC_B1_CLKREQN>;
bias-pull-up;
};
};
rt1715_int_pins: rt1715-int-pins {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
@ -814,9 +892,39 @@
};
};
&eth {
phy-mode ="rgmii-id";
phy-handle = <&ethernet_phy0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default_pins>;
pinctrl-1 = <&eth_sleep_pins>;
mediatek,mac-wol;
snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
snps,reset-delays-us = <0 10000 10000>;
status = "okay";
};
&eth_mdio {
ethernet_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
};
};
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
mt6359keys: keys {
compatible = "mediatek,mt6359-keys";
mediatek,long-press-mode = <1>;
power-off-time-sec = <0>;
power-key {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
};
};
&scp {
@ -824,6 +932,15 @@
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_pins>;
pinctrl-names = "default";
mediatek,pad-select = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
@ -842,15 +959,6 @@
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_pins>;
pinctrl-names = "default";
mediatek,pad-select = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&u3phy0 {
status = "okay";
};
@ -871,10 +979,28 @@
&xhci1 {
status = "okay";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_hub_reset_1v8>;
#address-cells = <1>;
#size-cells = <0>;
hub_2_0: hub@1 {
compatible = "usb451,8025";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&usb_hub_fixed_3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8027";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&usb_hub_fixed_3v3>;
};
};
&xhci2 {
status = "okay";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */
};

21
arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
View File

@ -187,13 +187,18 @@
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: eth-phy0@1 {
eth_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
};
};
};
&gpu {
mali-supply = <&mt6315_7_vbuck1>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
@ -337,6 +342,10 @@
domain-supply = <&mt6315_7_vbuck1>;
};
&mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
@ -407,6 +416,12 @@
regulator-always-on;
};
/* for GPU SRAM */
&mt6359_vsram_others_ldo_reg {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
};
&mt6359codec {
mediatek,mic-type-0 = <1>; /* ACC */
mediatek,mic-type-1 = <3>; /* DCC */
@ -839,8 +854,8 @@
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-min-microvolt = <546000>;
regulator-max-microvolt = <787000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};