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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (71 commits)
  MIPS: Lasat: Fix botched changes to sysctl code.
  RTC: rtc-cmos.c: Fix warning on MIPS
  MIPS: Cleanup random differences beween lmo and Linus' kernel.
  MIPS: No longer hardwire CONFIG_EMBEDDED to y
  MIPS: Fix and enhance built-in kernel command line
  MIPS: eXcite: Remove platform.
  MIPS: Loongson: Cleanups of serial port support
  MIPS: Lemote 2F: Suspend CS5536 MFGPT Timer
  MIPS: Excite: move iodev_remove to .devexit.text
  MIPS: Lasat: Convert to proc_fops / seq_file
  MIPS: Cleanup signal code initialization
  MIPS: Modularize COP2 handling
  MIPS: Move EARLY_PRINTK to Kconfig.debug
  MIPS: Yeeloong 2F: Cleanup reset logic using the new ec_write function
  MIPS: Yeeloong 2F: Add LID open event as the wakeup event
  MIPS: Yeeloong 2F: Add basic EC operations
  MIPS: Move several variables from .bss to .init.data
  MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address
  MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5
  MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer
  ...
This commit is contained in:
Linus Torvalds 2009-12-17 16:38:06 -08:00
commit dbfc985195
255 changed files with 18312 additions and 4880 deletions
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119
arch/mips/Kconfig
View File

@ -5,9 +5,12 @@ config MIPS
select HAVE_IDE
select HAVE_OPROFILE
select HAVE_ARCH_KGDB
# Horrible source of confusion. Die, die, die ...
select EMBEDDED
select RTC_LIB if !LEMOTE_FULOONG2E
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select RTC_LIB if !MACH_LOONGSON
mainmenu "Linux/MIPS Kernel Configuration"
@ -22,6 +25,7 @@ choice
config MACH_ALCHEMY
bool "Alchemy processor based machines"
select SYS_SUPPORTS_ZBOOT
config AR7
bool "Texas Instruments AR7"
@ -36,6 +40,7 @@ config AR7
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT_UART16550
select GENERIC_GPIO
select GCD
select VLYNQ
@ -43,23 +48,6 @@ config AR7
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_CPU_RM9K
select MIPS_RM9122
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The eXcite is a smart camera platform manufactured by
Basler Vision Technologies AG.
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
@ -192,6 +180,7 @@ config LASAT
config MACH_LOONGSON
bool "Loongson family of machines"
select SYS_SUPPORTS_ZBOOT_UART16550
help
This enables the support of Loongson family of machines.
@ -233,6 +222,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_MIPS_CMP
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_ZBOOT
help
This enables support for the MIPS Technologies Malta evaluation
board.
@ -334,6 +324,24 @@ config PMC_YOSEMITE
Yosemite is an evaluation board for the RM9000x2 processor
manufactured by PMC-Sierra.
config POWERTV
bool "Cisco PowerTV"
select BOOT_ELF32
select CEVT_R4K
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CSRC_POWERTV
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select USB_OHCI_LITTLE_ENDIAN
help
This enables support for the Cisco PowerTV Platform.
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select ARC
@ -674,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
endchoice
source "arch/mips/alchemy/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/powertv/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
@ -778,6 +786,9 @@ config CSRC_BCM1480
config CSRC_IOASIC
bool
config CSRC_POWERTV
bool
config CSRC_R4K_LIB
bool
@ -806,20 +817,6 @@ config DMA_NONCOHERENT
config DMA_NEED_PCI_MAP_STATE
bool
config EARLY_PRINTK
bool "Early printk" if EMBEDDED && DEBUG_KERNEL
depends on SYS_HAS_EARLY_PRINTK
default y
help
This option enables special console drivers which allow the kernel
to print messages very early in the bootup process.
This is useful for kernel debugging when your machine crashes very
early before the console code is initialized. For normal operation,
it is not recommended because it looks ugly on some machines and
doesn't cooperate with an X server. You should normally say N here,
unless you want to debug such a crash.
config SYS_HAS_EARLY_PRINTK
bool
@ -1069,6 +1066,21 @@ config CPU_LOONGSON2E
The Loongson 2E processor implements the MIPS III instruction set
with many extensions.
It has an internal FPGA northbridge, which is compatiable to
bonito64.
config CPU_LOONGSON2F
bool "Loongson 2F"
depends on SYS_HAS_CPU_LOONGSON2F
select CPU_LOONGSON2
help
The Loongson 2F processor implements the MIPS III instruction set
with many extensions.
Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
have a similar programming interface with FPGA northbridge used in
Loongson2E.
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@ -1294,6 +1306,16 @@ config CPU_CAVIUM_OCTEON
endchoice
config SYS_SUPPORTS_ZBOOT
bool
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_LZMA
config SYS_SUPPORTS_ZBOOT_UART16550
bool
select SYS_SUPPORTS_ZBOOT
config CPU_LOONGSON2
bool
select CPU_SUPPORTS_32BIT_KERNEL
@ -1303,6 +1325,12 @@ config CPU_LOONGSON2
config SYS_HAS_CPU_LOONGSON2E
bool
config SYS_HAS_CPU_LOONGSON2F
bool
select CPU_SUPPORTS_CPUFREQ
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
config SYS_HAS_CPU_MIPS32_R1
bool
@ -1411,8 +1439,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
bool
config CPU_SUPPORTS_64BIT_KERNEL
bool
config CPU_SUPPORTS_CPUFREQ
bool
config CPU_SUPPORTS_ADDRWINCFG
bool
config CPU_SUPPORTS_HUGEPAGES
bool
config CPU_SUPPORTS_UNCACHED_ACCELERATED
bool
config MIPS_PGD_C0_CONTEXT
bool
default y if 64BIT && CPU_MIPSR2
#
# Set to y for ptrace access to watch registers.
@ -2024,15 +2061,6 @@ config STACKTRACE_SUPPORT
source "init/Kconfig"
config PROBE_INITRD_HEADER
bool "Probe initrd header created by addinitrd"
depends on BLK_DEV_INITRD
help
Probe initrd header at the last page of kernel image.
Say Y here if you are using arch/mips/boot/addinitrd.c to
add initrd or initramfs image to the kernel image.
Otherwise, say N.
source "kernel/Kconfig.freezer"
menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@ -2104,6 +2132,7 @@ config MMU
config I8253
bool
select MIPS_EXTERNAL_TIMER
config ZONE_DMA32
bool
@ -2180,6 +2209,8 @@ source "kernel/power/Kconfig"
endmenu
source "arch/mips/kernel/cpufreq/Kconfig"
source "net/Kconfig"
source "drivers/Kconfig"

59
arch/mips/Kconfig.debug
View File

@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT
source "lib/Kconfig.debug"
config EARLY_PRINTK
bool "Early printk" if EMBEDDED
depends on SYS_HAS_EARLY_PRINTK
default y
help
This option enables special console drivers which allow the kernel
to print messages very early in the bootup process.
This is useful for kernel debugging when your machine crashes very
early before the console code is initialized. For normal operation,
it is not recommended because it looks ugly on some machines and
doesn't cooperate with an X server. You should normally say N here,
unless you want to debug such a crash.
config CMDLINE_BOOL
bool "Built-in kernel command line"
default n
help
For most systems, it is firmware or second stage bootloader that
by default specifies the kernel command line options. However,
it might be necessary or advantageous to either override the
default kernel command line or add a few extra options to it.
For such cases, this option allows you to hardcode your own
command line options directly into the kernel. For that, you
should choose 'Y' here, and fill in the extra boot arguments
in CONFIG_CMDLINE.
The built-in options will be concatenated to the default command
line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
command line will be ignored and replaced by the built-in string.
Most MIPS systems will normally expect 'N' here and rely upon
the command line from the firmware or the second-stage bootloader.
config CMDLINE
string "Default kernel command string"
depends on CMDLINE_BOOL
default ""
help
On some platforms, there is currently no way for the boot loader to
pass arguments to the kernel. For these platforms, you can supply
some command-line options at build time by entering them here. In
other cases you can specify kernel args so that you don't have
to set them up in board prom initialization routines.
pass arguments to the kernel. For these platforms, and for the cases
when you want to add some extra options to the command line or ignore
the default command line, you can supply some command-line options at
build time by entering them here. In other cases you can specify
kernel args so that you don't have to set them up in board prom
initialization routines.
For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
options.
config CMDLINE_OVERRIDE
bool "Built-in command line overrides firware arguments"
default n
depends on CMDLINE_BOOL
help
By setting this option to 'Y' you will have your kernel ignore
command line arguments from firmware or second stage bootloader.
Instead, the built-in command line will be used exclusively.
Normally, you will choose 'N' here.
config DEBUG_STACK_USAGE
bool "Enable stack utilization instrumentation"

57
arch/mips/Makefile
View File

@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH))
endif
endif
ifndef CONFIG_FUNCTION_TRACER
cflags-y := -ffunction-sections
endif
ifdef CONFIG_FUNCTION_GRAPH_TRACER
ifndef KBUILD_MCOUNT_RA_ADDRESS
ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
endif
endif
endif
cflags-y += $(call cc-option, -mno-check-zero-division)
ifdef CONFIG_32BIT
@ -69,6 +78,7 @@ endif
all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64)
all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
#
# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += \
$(call cc-option,-march=loongson2e,-march=r4600)
cflags-$(CONFIG_CPU_LOONGSON2F) += \
$(call cc-option,-march=loongson2f,-march=r4600)
cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
-Wa,-mips32 -Wa,--trap
@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
-mno-branch-likely
load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
#
# MIPS Malta board
@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
all-$(CONFIG_MIPS_MALTA) := vmlinuz.bin
#
# MIPS SIM
@ -355,13 +368,6 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/
cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
#
# Basler eXcite
#
core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
#
# LASAT platforms
#
@ -440,6 +446,13 @@ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
#
# Cisco PowerTV Platform
#
core-$(CONFIG_POWERTV) += arch/mips/powertv/
cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
load-$(CONFIG_POWERTV) += 0xffffffff90800000
#
# SGI IP22 (Indy/Indigo2)
#
@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80600000
else
load-$(CONFIG_SNI_RM) += 0xffffffff80030000
endif
all-$(CONFIG_SNI_RM) := vmlinux.ecoff
all-$(CONFIG_SNI_RM) := vmlinuz.ecoff
#
# Common TXx9
@ -699,9 +712,23 @@ vmlinux.64: vmlinux
$(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
all: $(all-y)
vmlinuz: vmlinux FORCE
+@$(call makezboot,$@)
vmlinuz.bin: vmlinux
+@$(call makezboot,$@)
vmlinuz.ecoff: vmlinux
+@$(call makezboot,$@)
vmlinuz.srec: vmlinux
+@$(call makezboot,$@)
vmlinux.bin: $(vmlinux-32)
+@$(call makeboot,$@)
@ -726,11 +753,13 @@ endif
install:
$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
$(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/boot/compressed
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
@ -738,10 +767,18 @@ define archhelp
echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'
echo ' vmlinuz - Compressed boot(zboot) image'
echo ' vmlinuz.ecoff - ECOFF zboot image'
echo ' vmlinuz.bin - Raw binary zboot image'
echo ' vmlinuz.srec - SREC zboot image'
echo
echo ' These will be default as apropriate for a configured platform.'
endef
CLEAN_FILES += vmlinux.32 \
vmlinux.64 \
vmlinux.ecoff
vmlinux.ecoff \
vmlinuz \
vmlinuz.ecoff \
vmlinuz.bin \
vmlinuz.srec

2
arch/mips/ar7/platform.c
View File

@ -505,7 +505,7 @@ static int __init ar7_register_devices(void)
int res;
u32 *bootcr, val;
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port[2];
static struct uart_port uart_port[2] __initdata;
memset(uart_port, 0, sizeof(struct uart_port) * 2);

9
arch/mips/basler/excite/Kconfig
View File

@ -1,9 +0,0 @@
config BASLER_EXCITE_PROTOTYPE
bool "Support for pre-release units"
depends on BASLER_EXCITE
default n
help
Pre-series (prototype) units are different from later ones in
some ways. Select this option if you have one of these. Please
note that a kernel built with this option selected will not be
able to run on normal units.

8
arch/mips/basler/excite/Makefile
View File

@ -1,8 +0,0 @@
#
# Makefile for Basler eXcite
#
obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
excite_device.o excite_procfs.o
obj-m += excite_iodev.o

403
arch/mips/basler/excite/excite_device.c
View File

@ -1,403 +0,0 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include <asm/types.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#include <rm9k_eth.h>
#include <rm9k_wdt.h>
#include <rm9k_xicap.h>
#include <excite_nandflash.h>
#include "excite_iodev.h"
#define RM9K_GE_UNIT 0
#define XICAP_UNIT 0
#define NAND_UNIT 0
#define DLL_TIMEOUT 3 /* seconds */
#define RINIT(__start__, __end__, __name__, __parent__) { \
.name = __name__ "_0", \
.start = (__start__), \
.end = (__end__), \
.flags = 0, \
.parent = (__parent__) \
}
#define RINIT_IRQ(__irq__, __name__) { \
.name = __name__ "_0", \
.start = (__irq__), \
.end = (__irq__), \
.flags = IORESOURCE_IRQ, \
.parent = NULL \
}
enum {
slice_xicap,
slice_eth
};
static struct resource
excite_ctr_resource __maybe_unused = {
.name = "GPI counters",
.start = 0,
.end = 5,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_gpislice_resource __maybe_unused = {
.name = "GPI slices",
.start = 0,
.end = 1,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_mdio_channel_resource __maybe_unused = {
.name = "MDIO channels",
.start = 0,
.end = 1,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_fifomem_resource __maybe_unused = {
.name = "FIFO memory",
.start = 0,
.end = 767,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_scram_resource __maybe_unused = {
.name = "Scratch RAM",
.start = EXCITE_PHYS_SCRAM,
.end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_fpga_resource __maybe_unused = {
.name = "System FPGA",
.start = EXCITE_PHYS_FPGA,
.end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_nand_resource __maybe_unused = {
.name = "NAND flash control",
.start = EXCITE_PHYS_NAND,
.end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_titan_resource __maybe_unused = {
.name = "TITAN registers",
.start = EXCITE_PHYS_TITAN,
.end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
};
static void adjust_resources(struct resource *res, unsigned int n)
{
struct resource *p;
const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA;
for (p = res; p < res + n; p++) {
const struct resource * const parent = p->parent;
if (parent) {
p->start += parent->start;
p->end += parent->start;
p->flags = parent->flags & mask;
}
}
}
#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
static struct resource xicap_rsrc[] = {
RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
};
static struct platform_device xicap_pdev = {
.name = XICAP_NAME,
.id = XICAP_UNIT,
.num_resources = ARRAY_SIZE(xicap_rsrc),
.resource = xicap_rsrc
};
/*
* Create a platform device for the GPI port that receives the
* image data from the embedded camera.
*/
static int __init xicap_devinit(void)
{
unsigned long tend;
u32 reg;
int retval;
adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
/* Power up the slice and configure it. */
reg = titan_readl(CPTC1R);
reg &= ~(0x11100 << slice_xicap);
titan_writel(reg, CPTC1R);
/* Enable slice & DLL. */
reg= titan_readl(CPRR);
reg &= ~(0x00030003 << (slice_xicap * 2));
titan_writel(reg, CPRR);
/* Wait for DLLs to lock */
tend = jiffies + DLL_TIMEOUT * HZ;
while (time_before(jiffies, tend)) {
if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
break;
yield();
}
if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
xicap_pdev.name, DLL_TIMEOUT);
retval = -ETIME;
} else {
/* Register platform device */
retval = platform_device_register(&xicap_pdev);
}
return retval;
}
device_initcall(xicap_devinit);
#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
static struct resource wdt_rsrc[] = {
RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
};
static struct platform_device wdt_pdev = {
.name = WDT_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(wdt_rsrc),
.resource = wdt_rsrc
};
/*
* Create a platform device for the GPI port that receives the
* image data from the embedded camera.
*/
static int __init wdt_devinit(void)
{
adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
return platform_device_register(&wdt_pdev);
}
device_initcall(wdt_devinit);
#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
static struct resource excite_nandflash_rsrc[] = {
RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
};
static struct platform_device excite_nandflash_pdev = {
.name = "excite_nand",
.id = NAND_UNIT,
.num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
.resource = excite_nandflash_rsrc
};
/*
* Create a platform device for the access to the nand-flash
* port
*/
static int __init excite_nandflash_devinit(void)
{
adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
/* nothing to be done here */
/* Register platform device */
return platform_device_register(&excite_nandflash_pdev);
}
device_initcall(excite_nandflash_devinit);
static struct resource iodev_rsrc[] = {
RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
};
static struct platform_device io_pdev = {
.name = IODEV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(iodev_rsrc),
.resource = iodev_rsrc
};
/*
* Create a platform device for the external I/O ports.
*/
static int __init io_devinit(void)
{
adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
return platform_device_register(&io_pdev);
}
device_initcall(io_devinit);
#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
static struct resource rm9k_ge_rsrc[] = {
RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
};
static struct platform_device rm9k_ge_pdev = {
.name = RM9K_GE_NAME,
.id = RM9K_GE_UNIT,
.num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
.resource = rm9k_ge_rsrc
};
/*
* Create a platform device for the Ethernet port.
*/
static int __init rm9k_ge_devinit(void)
{
u32 reg;
adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
/* Power up the slice and configure it. */
reg = titan_readl(CPTC1R);
reg &= ~(0x11000 << slice_eth);
reg |= 0x100 << slice_eth;
titan_writel(reg, CPTC1R);
/* Take the MAC out of reset, reset the DLLs. */
reg = titan_readl(CPRR);
reg &= ~(0x00030000 << (slice_eth * 2));
reg |= 0x3 << (slice_eth * 2);
titan_writel(reg, CPRR);
return platform_device_register(&rm9k_ge_pdev);
}
device_initcall(rm9k_ge_devinit);
#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
static int __init excite_setup_devs(void)
{
int res;
u32 reg;
/* Enable xdma and fifo interrupts */
reg = titan_readl(0x0050);
titan_writel(reg | 0x18000000, 0x0050);
res = request_resource(&iomem_resource, &excite_titan_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_scram_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_fpga_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_nand_resource);
if (res)
return res;
excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
( IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA);
excite_nand_resource.flags = excite_nand_resource.parent->flags &
( IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA);
return 0;
}
arch_initcall(excite_setup_devs);

178
arch/mips/basler/excite/excite_iodev.c
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@ -1,178 +0,0 @@
/*
* Copyright (C) 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/miscdevice.h>
#include <linux/smp_lock.h>
#include "excite_iodev.h"
static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
static int __init iodev_probe(struct platform_device *);
static int __exit iodev_remove(struct platform_device *);
static int iodev_open(struct inode *, struct file *);
static int iodev_release(struct inode *, struct file *);
static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
static irqreturn_t iodev_irqhdl(int, void *);
static const char iodev_name[] = "iodev";
static unsigned int iodev_irq;
static DECLARE_WAIT_QUEUE_HEAD(wq);
static const struct file_operations fops =
{
.owner = THIS_MODULE,
.open = iodev_open,
.release = iodev_release,
.read = iodev_read,
.poll = iodev_poll
};
static struct miscdevice miscdev =
{
.minor = MISC_DYNAMIC_MINOR,
.name = iodev_name,
.fops = &fops
};
static struct platform_driver iodev_driver = {
.driver = {
.name = iodev_name,
.owner = THIS_MODULE,
},
.probe = iodev_probe,
.remove = __devexit_p(iodev_remove),
};
static const struct resource *
iodev_get_resource(struct platform_device *pdv, const char *name,
unsigned int type)
{
char buf[80];
if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
return NULL;
return platform_get_resource_byname(pdv, type, buf);
}
/* No hotplugging on the platform bus - use __init */
static int __init iodev_probe(struct platform_device *dev)
{
const struct resource * const ri =
iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
if (unlikely(!ri))
return -ENXIO;
iodev_irq = ri->start;
return misc_register(&miscdev);
}
static int __exit iodev_remove(struct platform_device *dev)
{
return misc_deregister(&miscdev);
}
static int iodev_open(struct inode *i, struct file *f)
{
int ret;
ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
iodev_name, &miscdev);
return ret;
}
static int iodev_release(struct inode *i, struct file *f)
{
free_irq(iodev_irq, &miscdev);
return 0;
}
static ssize_t
iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
{
ssize_t ret;
DEFINE_WAIT(w);
prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
if (!signal_pending(current))
schedule();
ret = signal_pending(current) ? -ERESTARTSYS : 0;
finish_wait(&wq, &w);
return ret;
}
static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
{
poll_wait(f, &wq, p);
return POLLOUT | POLLWRNORM;
}
static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
{
wake_up(&wq);
return IRQ_HANDLED;
}
static int __init iodev_init_module(void)
{
return platform_driver_register(&iodev_driver);
}
static void __exit iodev_cleanup_module(void)
{
platform_driver_unregister(&iodev_driver);
}
module_init(iodev_init_module);
module_exit(iodev_cleanup_module);
MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
MODULE_VERSION("0.0");
MODULE_LICENSE("GPL");

10
arch/mips/basler/excite/excite_iodev.h
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@ -1,10 +0,0 @@
#ifndef __EXCITE_IODEV_H__
#define __EXCITE_IODEV_H__
/* Device name */
#define IODEV_NAME "iodev"
/* Resource names */
#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
#endif /* __EXCITE_IODEV_H__ */

122
arch/mips/basler/excite/excite_irq.c
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@ -1,122 +0,0 @@
/*
* Copyright (C) by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslereb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
extern asmlinkage void excite_handle_int(void);
/*
* Initialize the interrupt handler
*/
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
}
asmlinkage void plat_irq_dispatch(void)
{
const u32
interrupts = read_c0_cause() >> 8,
mask = ((read_c0_status() >> 8) & 0x000000ff) |
(read_c0_intcontrol() & 0x0000ff00),
pending = interrupts & mask;
u32 msgintflags, msgintmask, msgint;
/* process timer interrupt */
if (pending & (1 << TIMER_IRQ)) {
do_IRQ(TIMER_IRQ);
return;
}
/* Process PCI interrupts */
#if USB_IRQ < 10
msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
if ((pending & (1 << USB_IRQ)) && msgint) {
#else
if (pending & (1 << USB_IRQ)) {
#endif
do_IRQ(USB_IRQ);
return;
}
/* Process TITAN interrupts */
msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
if ((pending & (1 << TITAN_IRQ)) && msgint) {
ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
do_IRQ(TITAN_IRQ);
return;
}
/* Process FPGA line #0 interrupts */
msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
if ((pending & (1 << FPGA0_IRQ)) && msgint) {
do_IRQ(FPGA0_IRQ);
return;
}
/* Process FPGA line #1 interrupts */
msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
if ((pending & (1 << FPGA1_IRQ)) && msgint) {
do_IRQ(FPGA1_IRQ);
return;
}
/* Process PHY interrupts */
msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
if ((pending & (1 << PHY_IRQ)) && msgint) {
do_IRQ(PHY_IRQ);
return;
}
/* Process spurious interrupts */
spurious_interrupt();
}

92
arch/mips/basler/excite/excite_procfs.c
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@ -1,92 +0,0 @@
/*
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* Procfs support for Basler eXcite
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/stat.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
static int excite_unit_id_proc_show(struct seq_file *m, void *v)
{
seq_printf(m, "%06x", unit_id);
return 0;
}
static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, excite_unit_id_proc_show, NULL);
}
static const struct file_operations excite_unit_id_proc_fops = {
.owner = THIS_MODULE,
.open = excite_unit_id_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int
excite_bootrom_read(char *page, char **start, off_t off, int count,
int *eof, void *data)
{
void __iomem * src;
if (off >= EXCITE_SIZE_BOOTROM) {
*eof = 1;
return 0;
}
if ((off + count) > EXCITE_SIZE_BOOTROM)
count = EXCITE_SIZE_BOOTROM - off;
src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
if (src) {
memcpy_fromio(page, src, count);
iounmap(src);
*start = page;
} else {
count = -ENOMEM;
}
return count;
}
void excite_procfs_init(void)
{
/* Create & populate /proc/excite */
struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
if (pdir) {
struct proc_dir_entry * e;
e = proc_create("unit_id", S_IRUGO, pdir,
&excite_unit_id_proc_fops);
if (e) e->size = 6;
e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
excite_bootrom_read, NULL);
if (e) e->size = EXCITE_SIZE_BOOTROM;
}
}

144
arch/mips/basler/excite/excite_prom.c
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@ -1,144 +0,0 @@
/*
* Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
* Manish Lachwani.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/string.h>
#include <excite.h>
/* This struct is used by Redboot to pass arguments to the kernel */
typedef struct
{
char *name;
char *val;
} t_env_var;
struct parmblock {
t_env_var memsize;
t_env_var modetty0;
t_env_var ethaddr;
t_env_var env_end;
char *argv[2];
char text[0];
};
static unsigned int prom_argc;
static const char ** prom_argv;
static const t_env_var * prom_env;
static void prom_halt(void) __attribute__((noreturn));
static void prom_exit(void) __attribute__((noreturn));
const char *get_system_type(void)
{
return "Basler eXcite";
}
/*
* Halt the system
*/
static void prom_halt(void)
{
printk(KERN_NOTICE "\n** System halted.\n");
while (1)
asm volatile (
"\t.set\tmips3\n"
"\twait\n"
"\t.set\tmips0\n"
);
}
/*
* Reset the CPU and re-enter Redboot
*/
static void prom_exit(void)
{
unsigned int i;
volatile unsigned char * const flg =
(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
/* Clear the watchdog reset flag, set the reboot flag */
*flg &= ~0x01;
*flg |= 0x80;
for (i = 0; i < 10; i++) {
*(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
iob();
mdelay(1000);
}
printk(KERN_NOTICE "Reset failed\n");
prom_halt();
}
static const char __init *prom_getenv(char *name)
{
const t_env_var * p;
for (p = prom_env; p->name != NULL; p++)
if(strcmp(name, p->name) == 0)
break;
return p->val;
}
/*
* Init routine which accepts the variables from Redboot
*/
void __init prom_init(void)
{
const struct parmblock * const pb = (struct parmblock *) fw_arg2;
prom_argc = fw_arg0;
prom_argv = (const char **) fw_arg1;
prom_env = &pb->memsize;
/* Callbacks for halt, restart */
_machine_restart = (void (*)(char *)) prom_exit;
_machine_halt = prom_halt;
#ifdef CONFIG_32BIT
/* copy command line */
strcpy(arcs_cmdline, prom_argv[1]);
memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
strcpy(modetty, prom_getenv("modetty0"));
#endif /* CONFIG_32BIT */
#ifdef CONFIG_64BIT
# error 64 bit support not implemented
#endif /* CONFIG_64BIT */
}
/* This is called from free_initmem(), so we need to provide it */
void __init prom_free_prom_memory(void)
{
/* Nothing to do */
}

302
arch/mips/basler/excite/excite_setup.c
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@ -1,302 +0,0 @@
/*
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
* Manish Lachwani.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/pgtable-32.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#define TITAN_UART_CLK 25000000
#if 1
/* normal serial port assignment */
#define REGBASE_SER0 0x0208
#define REGBASE_SER1 0x0238
#define MASK_SER0 0x1
#define MASK_SER1 0x2
#else
/* serial ports swapped */
#define REGBASE_SER0 0x0238
#define REGBASE_SER1 0x0208
#define MASK_SER0 0x2
#define MASK_SER1 0x1
#endif
unsigned long memsize;
char modetty[30];
unsigned int titan_irq = TITAN_IRQ;
static void __iomem * ctl_regs;
u32 unit_id;
volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
/* Protect access to shared GPI registers */
DEFINE_SPINLOCK(titan_lock);
int titan_irqflags;
/*
* The eXcite platform uses the alternate timer interrupt
*
* Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
* to handle the alternate timer interrupt of the RM9000.
*/
void __init plat_time_init(void)
{
const u32 modebit5 = ocd_readl(0x00e4);
unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
if (div == 33)
div = 1;
mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
}
static int __init excite_init_console(void)
{
#if defined(CONFIG_SERIAL_8250)
static __initdata char serr[] =
KERN_ERR "Serial port #%u setup failed\n";
struct uart_port up;
/* Take the DUART out of reset */
titan_writel(0x00ff1cff, CPRR);
#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
/* Enable both ports */
titan_writel(MASK_SER0 | MASK_SER1, UACFG);
#else
/* Enable port #0 only */
titan_writel(MASK_SER0, UACFG);
#endif
/*
* Set up serial port #0. Do not use autodetection; the result is
* not what we want.
*/
memset(&up, 0, sizeof(up));
up.membase = (char *) titan_addr(REGBASE_SER0);
up.irq = TITAN_IRQ;
up.uartclk = TITAN_UART_CLK;
up.regshift = 0;
up.iotype = UPIO_RM9000;
up.type = PORT_RM9000;
up.flags = UPF_SHARE_IRQ;
up.line = 0;
if (early_serial_setup(&up))
printk(serr, up.line);
#if CONFIG_SERIAL_8250_NR_UARTS > 1
/* And now for port #1. */
up.membase = (char *) titan_addr(REGBASE_SER1);
up.line = 1;
if (early_serial_setup(&up))
printk(serr, up.line);
#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
#else
/* Leave the DUART in reset */
titan_writel(0x00ff3cff, CPRR);
#endif /* defined(CONFIG_SERIAL_8250) */
return 0;
}
static int __init excite_platform_init(void)
{
unsigned int i;
unsigned char buf[3];
u8 reg;
void __iomem * dpr;
/* BIU buffer allocations */
ocd_writel(8, CPURSLMT); /* CPU */
titan_writel(4, CPGRWL); /* GPI / Ethernet */
/* Map control registers located in FPGA */
ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
if (!ctl_regs)
panic("eXcite: failed to map platform control registers\n");
memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
/* Clear the reboot flag */
dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
reg = __raw_readb(dpr);
__raw_writeb(reg & 0x7f, dpr);
iounmap(dpr);
/* Interrupt controller setup */
for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
ocd_writel(0x00000000, i + 0x04);
ocd_writel(0xffffffff, i + 0x0c);
}
ocd_writel(0x2, NMICONFIG);
ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
ocd_writel((0x1 << (PHY_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
#if USB_IRQ < 10
ocd_writel((0x1 << (USB_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
#endif
/* Enable the packet FIFO, XDMA and XDMA arbiter */
titan_writel(0x00ff18ff, CPRR);
/*
* Set up the PADMUX. Power down all ethernet slices,
* they will be powered up and configured at device startup.
*/
titan_writel(0x00878206, CPTC1R);
titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
/* Reset and enable the FIFO block */
titan_writel(0x00000001, SDRXFCIE);
titan_writel(0x00000001, SDTXFCIE);
titan_writel(0x00000100, SDRXFCIE);
titan_writel(0x00000000, SDTXFCIE);
/*
* Initialize the common interrupt shared by all components of
* the GPI/Ethernet subsystem.
*/
titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
titan_writel(TITAN_MSGINT, CPCFG1);
/*
* XDMA configuration.
* In order for the XDMA to be sharable among multiple drivers,
* the setup must be done here in the platform. The reason is that
* this setup can only be done while the XDMA is in reset. If this
* were done in a driver, it would interrupt all other drivers
* using the XDMA.
*/
titan_writel(0x80021dff, GXCFG); /* XDMA reset */
titan_writel(0x00000000, CPXCISRA);
titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
#if defined(CONFIG_HIGHMEM)
# error change for HIGHMEM support!
#else
titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
#endif
titan_writel(0, GXDMA_DESCADR);
for (i = 0x5040; i <= 0x5300; i += 0x0040)
titan_writel(0x80080000, i); /* reset channel */
titan_writel((0x1 << 29) /* no sparse tx descr. */
| (0x1 << 28) /* no sparse rx descr. */
| (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
| (0x1 << 21) | (0x1 << 22) /* data coherency */
| (0x1 << 17)
| 0x1dff,
GXCFG);
#if defined(CONFIG_SMP)
# error No SMP support
#else
/* All interrupts go to core #0 only. */
titan_writel(0x1f007fff, CPDST0A);
titan_writel(0x00000000, CPDST0B);
titan_writel(0x0000ff3f, CPDST1A);
titan_writel(0x00000000, CPDST1B);
titan_writel(0x00ffffff, CPXDSTA);
titan_writel(0x00000000, CPXDSTB);
#endif
/* Enable DUART interrupts, disable everything else. */
titan_writel(0x04000000, CPGIG0ER);
titan_writel(0x000000c0, CPGIG1ER);
excite_procfs_init();
return 0;
}
void __init plat_mem_setup(void)
{
volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
/* Announce RAM to system */
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
/* Set up the peripheral address map */
*(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
wmb();
*(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
wmb();
ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
/* Local bus slot #0 */
ocd_writel(0x00040510, LDP0);
ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
/* Local bus slot #2 */
ocd_writel(0x00000330, LDP2);
ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
/* Local bus slot #3 */
ocd_writel(0x00123413, LDP3);
ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
}
console_initcall(excite_init_console);
arch_initcall(excite_platform_init);
EXPORT_SYMBOL(titan_lock);
EXPORT_SYMBOL(titan_irqflags);
EXPORT_SYMBOL(titan_irq);
EXPORT_SYMBOL(ocd_base);
EXPORT_SYMBOL(titan_base);

10
arch/mips/bcm47xx/prom.c
View File

@ -100,11 +100,11 @@ static __init void prom_init_console(void)
static __init void prom_init_cmdline(void)
{
static char buf[CL_SIZE] __initdata;
static char buf[COMMAND_LINE_SIZE] __initdata;
/* Get the kernel command line from CFE */
if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
buf[CL_SIZE-1] = 0;
if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
buf[COMMAND_LINE_SIZE - 1] = 0;
strcpy(arcs_cmdline, buf);
}
@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void)
* as CFE is not available anymore later in the boot process. */
if ((strstr(arcs_cmdline, "console=")) == NULL) {
/* Try to read the default serial port used by CFE */
if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
|| (strncmp("uart", buf, 4)))
/* Default to uart0 */
strcpy(buf, "uart0");
/* Compute the new command line */
snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
arcs_cmdline, buf[4]);
}
}

8
arch/mips/boot/Makefile
View File

@ -25,7 +25,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections))
VMLINUX = vmlinux
all: vmlinux.ecoff vmlinux.srec addinitrd
all: vmlinux.ecoff vmlinux.srec
vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
$(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX)
vmlinux.srec: $(VMLINUX)
$(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
$(obj)/addinitrd: $(obj)/addinitrd.c
$(HOSTCC) -o $@ $^
clean-files += addinitrd \
elf2ecoff \
clean-files += elf2ecoff \
vmlinux.bin \
vmlinux.ecoff \
vmlinux.srec

131
arch/mips/boot/addinitrd.c
View File

@ -1,131 +0,0 @@
/*
* addinitrd - program to add a initrd image to an ecoff kernel
*
* (C) 1999 Thomas Bogendoerfer
* minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
* further cleanup: Maciej W. Rozycki
*/
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <stdio.h>
#include <netinet/in.h>
#include "ecoff.h"
#define MIPS_PAGE_SIZE 4096
#define MIPS_PAGE_MASK (MIPS_PAGE_SIZE-1)
#define swab16(x) \
((unsigned short)( \
(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
(((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
#define swab32(x) \
((unsigned int)( \
(((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
(((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
#define SWAB(a) (swab ? swab32(a) : (a))
void die(char *s)
{
perror(s);
exit(1);
}
int main(int argc, char *argv[])
{
int fd_vmlinux, fd_initrd, fd_outfile;
FILHDR efile;
AOUTHDR eaout;
SCNHDR esecs[3];
struct stat st;
char buf[1024];
unsigned long loadaddr;
unsigned long initrd_header[2];
int i, cnt;
int swab = 0;
if (argc != 4) {
printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
exit(1);
}
if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
die("open vmlinux");
if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
die("read file header");
if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
die("read aout header");
if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
die("read section headers");
/*
* check whether the file is good for us
*/
/* TBD */
/*
* check, if we have to swab words
*/
if (ntohs(0xaa55) == 0xaa55) {
if (efile.f_magic == swab16(MIPSELMAGIC))
swab = 1;
} else {
if (efile.f_magic == swab16(MIPSEBMAGIC))
swab = 1;
}
/* make sure we have an empty data segment for the initrd */
if (eaout.dsize || esecs[1].s_size) {
fprintf(stderr, "Data segment not empty. Giving up!\n");
exit(1);
}
if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
die("open initrd");
if (fstat (fd_initrd, &st) < 0)
die("fstat initrd");
loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
+ MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
loadaddr += MIPS_PAGE_SIZE;
initrd_header[0] = SWAB(0x494E5244);
initrd_header[1] = SWAB(st.st_size);
eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
die("open outfile");
if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
die("write file header");
if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
die("write aout header");
if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
die("write section headers");
/* skip padding */
if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
die("lseek vmlinux");
if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
die("lseek outfile");
/* copy text segment */
cnt = SWAB(eaout.tsize);
while (cnt) {
if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
die("read vmlinux");
if (write (fd_outfile, buf, i) != i)
die("write vmlinux");
cnt -= i;
}
if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
die("write initrd header");
while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
if (write (fd_outfile, buf, i) != i)
die("write initrd");
close(fd_vmlinux);
close(fd_initrd);
return 0;
}

100
arch/mips/boot/compressed/Makefile Normal file
View File

@ -0,0 +1,100 @@
#
# This file is subject to the terms and conditions of the GNU General Public
# License.
#
# Adapted for MIPS Pete Popov, Dan Malek
#
# Copyright (C) 1994 by Linus Torvalds
# Adapted for PowerPC by Gary Thomas
# modified by Cort (cort@cs.nmt.edu)
#
# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
# Author: Wu Zhangjin <wuzj@lemote.com>
#
# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
# set the default size of the mallocing area for decompressing
BOOT_HEAP_SIZE := 0x400000
# Disable Function Tracer
KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
$(call if_changed,objcopy)
suffix_$(CONFIG_KERNEL_GZIP) = gz
suffix_$(CONFIG_KERNEL_BZIP2) = bz2
suffix_$(CONFIG_KERNEL_LZMA) = lzma
tool_$(CONFIG_KERNEL_GZIP) = gzip
tool_$(CONFIG_KERNEL_BZIP2) = bzip2
tool_$(CONFIG_KERNEL_LZMA) = lzma
$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
$(call if_changed,$(tool_y))
$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
$(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
--add-section=.image=$< \
--set-section-flags=.image=contents,alloc,load,readonly,data \
$(obj)/dummy.o $@
LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
$(call if_changed,ld)
$(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@
#
# Some DECstations need all possible sections of an ECOFF executable
#
ifdef CONFIG_MACH_DECSTATION
E2EFLAGS = -a
else
E2EFLAGS =
endif
# elf2ecoff can only handle 32bit image
ifdef CONFIG_32BIT
VMLINUZ = vmlinuz
else
VMLINUZ = vmlinuz.32
endif
vmlinuz.32: vmlinuz
$(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
$(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
$(Q)$(HOSTCC) -o $@ $^
drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
strip-flags = $(addprefix --remove-section=,$(drop-sections))
OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags)
vmlinuz.bin: vmlinuz
$(call if_changed,objcopy)
OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags)
vmlinuz.srec: vmlinuz
$(call if_changed,objcopy)
clean:
clean-files += *.o \
vmlinu*

37
arch/mips/boot/compressed/dbg.c Normal file
View File

@ -0,0 +1,37 @@
/*
* MIPS-specific debug support for pre-boot environment
*
* NOTE: putc() is board specific, if your board have a 16550 compatible uart,
* please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
* need to implement your own putc().
*/
#include <linux/init.h>
#include <linux/types.h>
void __attribute__ ((weak)) putc(char c)
{
}
void puts(const char *s)
{
char c;
while ((c = *s++) != '\0') {
putc(c);
if (c == '\n')
putc('\r');
}
}
void puthex(unsigned long long val)
{
unsigned char buf[10];
int i;
for (i = 7; i >= 0; i--) {
buf[i] = "0123456789ABCDEF"[val & 0x0F];
val >>= 4;
}
buf[8] = '\0';
puts(buf);
}

126
arch/mips/boot/compressed/decompress.c Normal file
View File

@ -0,0 +1,126 @@
/*
* Misc. bootloader code for many machines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Matt Porter <mporter@mvista.com> Derived from
* arch/ppc/boot/prep/misc.c
*
* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
* Author: Wu Zhangjin <wuzj@lemote.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/addrspace.h>
/* These two variables specify the free mem region
* that can be used for temporary malloc area
*/
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
char *zimage_start;
/* The linker tells us where the image is. */
extern unsigned char __image_begin, __image_end;
extern unsigned char __ramdisk_begin, __ramdisk_end;
unsigned long initrd_size;
/* debug interfaces */
extern void puts(const char *s);
extern void puthex(unsigned long long val);
void error(char *x)
{
puts("\n\n");
puts(x);
puts("\n\n -- System halted");
while (1)
; /* Halt */
}
/* activate the code for pre-boot environment */
#define STATIC static
#ifdef CONFIG_KERNEL_GZIP
void *memcpy(void *dest, const void *src, size_t n)
{
int i;
const char *s = src;
char *d = dest;
for (i = 0; i < n; i++)
d[i] = s[i];
return dest;
}
#include "../../../../lib/decompress_inflate.c"
#endif
#ifdef CONFIG_KERNEL_BZIP2
void *memset(void *s, int c, size_t n)
{
int i;
char *ss = s;
for (i = 0; i < n; i++)
ss[i] = c;
return s;
}
#include "../../../../lib/decompress_bunzip2.c"
#endif
#ifdef CONFIG_KERNEL_LZMA
#include "../../../../lib/decompress_unlzma.c"
#endif
void decompress_kernel(unsigned long boot_heap_start)
{
int zimage_size;
/*
* We link ourself to an arbitrary low address. When we run, we
* relocate outself to that address. __image_beign points to
* the part of the image where the zImage is. -- Tom
*/
zimage_start = (char *)(unsigned long)(&__image_begin);
zimage_size = (unsigned long)(&__image_end) -
(unsigned long)(&__image_begin);
/*
* The zImage and initrd will be between start and _end, so they've
* already been moved once. We're good to go now. -- Tom
*/
puts("zimage at: ");
puthex((unsigned long)zimage_start);
puts(" ");
puthex((unsigned long)(zimage_size + zimage_start));
puts("\n");
if (initrd_size) {
puts("initrd at: ");
puthex((unsigned long)(&__ramdisk_begin));
puts(" ");
puthex((unsigned long)(&__ramdisk_end));
puts("\n");
}
/* this area are prepared for mallocing when decompressing */
free_mem_ptr = boot_heap_start;
free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
/* Display standard Linux/MIPS boot prompt for kernel args */
puts("Uncompressing Linux at load address ");
puthex(VMLINUX_LOAD_ADDRESS_ULL);
puts("\n");
/* Decompress the kernel with according algorithm */
decompress(zimage_start, zimage_size, 0, 0,
(void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
/* FIXME: is there a need to flush cache here? */
puts("Now, booting the kernel...\n");
}

4
arch/mips/boot/compressed/dummy.c Normal file
View File

@ -0,0 +1,4 @@
int main(void)
{
return 0;
}

56
arch/mips/boot/compressed/head.S Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995 Waldorf Electronics
* Written by Ralf Baechle and Andreas Busse
* Copyright (C) 1995 - 1999 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Modified for DECStation and hence R3000 support by Paul M. Antoine
* Further modifications by David S. Miller and Harald Koerfgen
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
.set noreorder
.cprestore
LEAF(start)
start:
/* Save boot rom start args */
move s0, a0
move s1, a1
move s2, a2
move s3, a3
/* Clear BSS */
PTR_LA a0, _edata
PTR_LA a2, _end
1: sw zero, 0(a0)
bne a2, a0, 1b
addiu a0, a0, 4
PTR_LA a0, (.heap) /* heap address */
PTR_LA sp, (.stack + 8192) /* stack address */
PTR_LA ra, 2f
PTR_LA k0, decompress_kernel
jr k0
nop
2:
move a0, s0
move a1, s1
move a2, s2
move a3, s3
PTR_LI k0, KERNEL_ENTRY
jr k0
nop
3:
b 3b
nop
END(start)
.comm .heap,BOOT_HEAP_SIZE,4
.comm .stack,4096*2,4

150
arch/mips/boot/compressed/ld.script Normal file
View File

@ -0,0 +1,150 @@
OUTPUT_ARCH(mips)
ENTRY(start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.init : { *(.init) } =0
.text :
{
_ftext = . ;
*(.text)
*(.rodata)
*(.rodata1)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} =0
.kstrtab : { *(.kstrtab) }
. = ALIGN(16); /* Exception table */
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
__start___dbe_table = .; /* Exception table for data bus errors */
__dbe_table : { *(__dbe_table) }
__stop___dbe_table = .;
__start___ksymtab = .; /* Kernel symbol table */
__ksymtab : { *(__ksymtab) }
__stop___ksymtab = .;
_etext = .;
. = ALIGN(8192);
.data.init_task : { *(.data.init_task) }
/* Startup code */
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(16);
__setup_start = .;
.setup.init : { *(.setup.init) }
__setup_end = .;
__initcall_start = .;
.initcall.init : { *(.initcall.init) }
__initcall_end = .;
. = ALIGN(4096); /* Align double page for init_task_union */
__init_end = .;
. = ALIGN(4096);
.data.page_aligned : { *(.data.idt) }
. = ALIGN(32);
.data.cacheline_aligned : { *(.data.cacheline_aligned) }
.fini : { *(.fini) } =0
.reginfo : { *(.reginfo) }
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
. = .;
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
. = .;
.data :
{
_fdata = . ;
*(.data)
/* Put the compressed image here, so bss is on the end. */
__image_begin = .;
*(.image)
__image_end = .;
/* Align the initial ramdisk image (INITRD) on page boundaries. */
. = ALIGN(4096);
__ramdisk_begin = .;
*(.initrd)
__ramdisk_end = .;
. = ALIGN(4096);
CONSTRUCTORS
}
.data1 : { *(.data1) }
_gp = . + 0x8000;
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
.got : { *(.got.plt) *(.got) }
.dynamic : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata : { *(.sdata) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
_fbss = .;
.sbss : { *(.sbss) *(.scommon) }
.bss :
{
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}
/* Sections to be discarded */
/DISCARD/ :
{
*(.text.exit)
*(.data.exit)
*(.exitcall.exit)
}
/* This is the MIPS specific mdebug section. */
.mdebug : { *(.mdebug) }
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the .debug DWARF section are relative to the beginning of the
section so we begin .debug at 0. It's not clear yet what needs to happen
for the others. */
.debug 0 : { *(.debug) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.line 0 : { *(.line) }
/* These must appear regardless of . */
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
.comment : { *(.comment) }
.note : { *(.note) }
}

43
arch/mips/boot/compressed/uart-16550.c Normal file
View File

@ -0,0 +1,43 @@
/*
* 16550 compatible uart based serial debug support for zboot
*/
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
#define UART_BASE 0x1fd003f8
#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
#endif
#ifdef CONFIG_AR7
#include <ar7.h>
#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
#endif
#ifndef PORT
#error please define the serial port address for your own machine
#endif
static inline unsigned int serial_in(int offset)
{
return *((char *)PORT(offset));
}
static inline void serial_out(int offset, int value)
{
*((char *)PORT(offset)) = value;
}
void putc(char c)
{
int timeout = 1024;
while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
;
serial_out(UART_TX, c);
}

2
arch/mips/cavium-octeon/Makefile
View File

@ -9,7 +9,7 @@
# Copyright (C) 2005-2009 Cavium Networks
#
obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o

52
arch/mips/cavium-octeon/cpu.c Normal file
View File

@ -0,0 +1,52 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#include <linux/init.h>
#include <linux/irqflags.h>
#include <linux/notifier.h>
#include <linux/prefetch.h>
#include <linux/sched.h>
#include <asm/cop2.h>
#include <asm/current.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/octeon/octeon.h>
static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
void *data)
{
unsigned long flags;
unsigned int status;
switch (action) {
case CU2_EXCEPTION:
prefetch(&current->thread.cp2);
local_irq_save(flags);
KSTK_STATUS(current) |= ST0_CU2;
status = read_c0_status();
write_c0_status(status | ST0_CU2);
octeon_cop2_restore(&(current->thread.cp2));
write_c0_status(status & ~ST0_CU2);
local_irq_restore(flags);
return NOTIFY_BAD; /* Don't call default notifier */
}
return NOTIFY_OK; /* Let default notifier send signals */
}
static struct notifier_block cnmips_cu2_notifier = {
.notifier_call = cnmips_cu2_call,
};
static int cnmips_cu2_setup(void)
{
return register_cu2_notifier(&cnmips_cu2_notifier);
}
early_initcall(cnmips_cu2_setup);

88
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -159,6 +159,94 @@ out:
}
device_initcall(octeon_rng_device_init);
/* Octeon SMI/MDIO interface. */
static int __init octeon_mdiobus_device_init(void)
{
struct platform_device *pd;
int ret = 0;
if (octeon_is_simulation())
return 0; /* No mdio in the simulator. */
/* The bus number is the platform_device id. */
pd = platform_device_alloc("mdio-octeon", 0);
if (!pd) {
ret = -ENOMEM;
goto out;
}
ret = platform_device_add(pd);
if (ret)
goto fail;
return ret;
fail:
platform_device_put(pd);
out:
return ret;
}
device_initcall(octeon_mdiobus_device_init);
/* Octeon mgmt port Ethernet interface. */
static int __init octeon_mgmt_device_init(void)
{
struct platform_device *pd;
int ret = 0;
int port, num_ports;
struct resource mgmt_port_resource = {
.flags = IORESOURCE_IRQ,
.start = -1,
.end = -1
};
if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
return 0;
if (OCTEON_IS_MODEL(OCTEON_CN56XX))
num_ports = 1;
else
num_ports = 2;
for (port = 0; port < num_ports; port++) {
pd = platform_device_alloc("octeon_mgmt", port);
if (!pd) {
ret = -ENOMEM;
goto out;
}
switch (port) {
case 0:
mgmt_port_resource.start = OCTEON_IRQ_MII0;
break;
case 1:
mgmt_port_resource.start = OCTEON_IRQ_MII1;
break;
default:
BUG();
}
mgmt_port_resource.end = mgmt_port_resource.start;
ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
if (ret)
goto fail;
ret = platform_device_add(pd);
if (ret)
goto fail;
}
return ret;
fail:
platform_device_put(pd);
out:
return ret;
}
device_initcall(octeon_mgmt_device_init);
MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Platform driver for Octeon SOC");

4
arch/mips/configs/ar7_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_MIPS=y
#
# CONFIG_MACH_ALCHEMY is not set
CONFIG_AR7=y
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="deadline"
CONFIG_PROBE_INITRD_HEADER=y
# CONFIG_FREEZER is not set
#
@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/bcm47xx_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
CONFIG_BCM47XX=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/bcm63xx_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
CONFIG_BCM63XX=y
# CONFIG_MIPS_COBALT is not set
@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,115200"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/bigsur_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SB1XXX_CORELIS is not set
# CONFIG_RUNTIME_DEBUG is not set

3
arch/mips/configs/capcella_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

4
arch/mips/configs/cavium-octeon_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# CONFIG_PROBE_INITRD_HEADER is not set
# CONFIG_FREEZER is not set
#
@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set

3
arch/mips/configs/cobalt_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
CONFIG_MIPS_COBALT=y
# CONFIG_MACH_DECSTATION is not set
@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/db1000_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/db1100_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/db1200_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
# CONFIG_MIPS_DB1550 is not set
CONFIG_MIPS_DB1200=y
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="mem=48M"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/db1500_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/db1550_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_DB1550=y
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/decstation_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
CONFIG_MACH_DECSTATION=y
# CONFIG_MACH_JAZZ is not set
@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/e55_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

1335
arch/mips/configs/excite_defconfig
View File

File diff suppressed because it is too large Load Diff

96
arch/mips/configs/fuloong2e_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.31-rc1
# Thu Jul 2 22:37:00 2009
# Linux kernel version: 2.6.32-rc4
# Fri Oct 16 13:18:01 2009
#
CONFIG_MIPS=y
@ -10,8 +10,8 @@ CONFIG_MIPS=y
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_AR7 is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
CONFIG_CPU_LOONGSON2=y
CONFIG_SYS_HAS_CPU_LOONGSON2E=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_FLATMEM_MANUAL is not set
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_STATIC=y
#
# Memory hotplug is currently incompatible with Software Suspend
#
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_PHYS_ADDR_T_64BIT=y
@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION="-fuloong2e"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=64
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@ -235,18 +249,16 @@ CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Performance Counters
# Kernel Performance Events And Counters
#
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_MARKERS=y
CONFIG_OPROFILE=m
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_SYSCALL_WRAPPERS=y
@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLOW_WORK=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_FREEZER is not set
CONFIG_FREEZER=y
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP=y
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_HIBERNATION_NVS=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION="/dev/hda3"
# CONFIG_PM_RUNTIME is not set
CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
#
# Networking options
@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y
# CONFIG_AF_RXRPC is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
CONFIG_CFG80211_DEFAULT_PS_VALUE=0
CONFIG_WIRELESS_OLD_REGULATORY=y
CONFIG_WIRELESS_EXT=y
CONFIG_WIRELESS_EXT_SYSFS=y
@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y
#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_MAC80211_DEFAULT_PS_VALUE=0
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
CONFIG_NET_9P=m
@ -495,6 +513,7 @@ CONFIG_NET_9P=m
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE=""
# CONFIG_CONNECTOR is not set
CONFIG_MTD=m
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_PARTITIONS is not set
# CONFIG_MTD_TESTS is not set
#
# User Modules And Translation Layers
@ -820,6 +839,7 @@ CONFIG_8139TOO=y
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_KS8842 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_SC92031 is not set
# CONFIG_ATL2 is not set
@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
# CONFIG_SFC is not set
# CONFIG_BE2NET is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
CONFIG_WLAN=y
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_CDC_PHONET is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_SERIAL=y
# CONFIG_MOUSE_APPLETOUCH is not set
@ -1015,6 +1038,7 @@ CONFIG_RTC=y
CONFIG_DEVPORT=y
CONFIG_I2C=m
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_HELPER_AUTO=y
@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y
#
# Graphics support
#
CONFIG_VGA_ARB=y
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y
# CONFIG_LOGO is not set
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
CONFIG_HIDRAW=y
#
@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_ISP1760_HCD=m
# CONFIG_USB_ISP1362_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m
# CONFIG_UIO_SMX is not set
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
#
# TI VLYNQ
@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=m
CONFIG_EXT4DEV_COMPAT=y
CONFIG_EXT4_FS_XATTR=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_FS_XIP=y
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=2048
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options
@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m
#
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
CONFIG_CRYPTO_GHASH=m
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=m
# CONFIG_CRYPTO_MICHAEL_MIC is not set

3
arch/mips/configs/ip22_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DYNAMIC_PRINTK_DEBUG=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/ip27_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -940,7 +939,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/ip28_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/ip32_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/jazz_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
CONFIG_MACH_JAZZ=y
@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/jmr3927_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/lasat_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

1835
arch/mips/configs/lemote2f_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

3
arch/mips/configs/malta_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_MIPS=y
#
CONFIG_ZONE_DMA=y
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/markeins_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/mipssim_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set

3
arch/mips/configs/mpc30x_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/msp71xx_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set
# CONFIG_MIPS_UNCACHED is not set

3
arch/mips/configs/mtx1_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/pb1100_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/pb1500_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/pb1550_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/pnx8335-stb225_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
# CONFIG_KERNEL_TESTS is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/pnx8550-jbs_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set

3
arch/mips/configs/pnx8550-stb810_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set

1550
arch/mips/configs/powertv_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

3
arch/mips/configs/rb532_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

4
arch/mips/configs/rbtx49xx_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_MIPS=y
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_AR7 is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
# CONFIG_MIPS_COBALT is not set
@ -284,7 +283,6 @@ CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_PROBE_INITRD_HEADER is not set
# CONFIG_FREEZER is not set
#
@ -1063,7 +1061,7 @@ CONFIG_TRACING_SUPPORT=y
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/rm200_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
#
# Security options

3
arch/mips/configs/sb1250-swarm_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_SB1XXX_CORELIS is not set
#

3
arch/mips/configs/tb0219_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/tb0226_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/tb0287_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/workpad_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MIPS=y
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/wrppmc_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,115200n8"
# CONFIG_CMDLINE_OVERRIDE is not set
#
# Security options

3
arch/mips/configs/yosemite_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_RUNTIME_DEBUG is not set

5
arch/mips/fw/arc/cmdline.c
View File

@ -16,11 +16,6 @@
#undef DEBUG_CMDLINE
char * __init prom_getcmdline(void)
{
return arcs_cmdline;
}
static char *ignored[] = {
"ConsoleIn=",
"ConsoleOut=",

8
arch/mips/include/asm/bootinfo.h
View File

@ -67,9 +67,9 @@
#define MACH_LEMOTE_ML2F7 3
#define MACH_LEMOTE_YL2F89 4
#define MACH_DEXXON_GDIUM2F10 5
#define MACH_LOONGSON_END 6
#define CL_SIZE COMMAND_LINE_SIZE
#define MACH_LEMOTE_NAS 6
#define MACH_LEMOTE_LL2F 7
#define MACH_LOONGSON_END 8
extern char *system_type;
const char *get_system_type(void);
@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
/*
* Initial kernel command line, usually setup by prom_init()
*/
extern char arcs_cmdline[CL_SIZE];
extern char arcs_cmdline[COMMAND_LINE_SIZE];
/*
* Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware

64
arch/mips/include/asm/clock.h Normal file
View File

@ -0,0 +1,64 @@
#ifndef __ASM_MIPS_CLOCK_H
#define __ASM_MIPS_CLOCK_H
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
extern void (*cpu_wait) (void);
struct clk;
struct clk_ops {
void (*init) (struct clk *clk);
void (*enable) (struct clk *clk);
void (*disable) (struct clk *clk);
void (*recalc) (struct clk *clk);
int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
long (*round_rate) (struct clk *clk, unsigned long rate);
};
struct clk {
struct list_head node;
const char *name;
int id;
struct module *owner;
struct clk *parent;
struct clk_ops *ops;
struct kref kref;
unsigned long rate;
unsigned long flags;
};
#define CLK_ALWAYS_ENABLED (1 << 0)
#define CLK_RATE_PROPAGATES (1 << 1)
/* Should be defined by processor-specific code */
void arch_init_clk_ops(struct clk_ops **, int type);
int clk_init(void);
int __clk_enable(struct clk *);
void __clk_disable(struct clk *);
void clk_recalc_rate(struct clk *);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
/* the exported API, in addition to clk_set_rate */
/**
* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
* @clk: clock source
* @rate: desired clock rate in Hz
* @algo_id: algorithm id to be passed down to ops->set_rate
*
* Returns success (0) or negative errno.
*/
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
#endif /* __ASM_MIPS_CLOCK_H */

23
arch/mips/include/asm/cop2.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_COP2_H
#define __ASM_COP2_H
enum cu2_ops {
CU2_EXCEPTION,
CU2_LWC2_OP,
CU2_LDC2_OP,
CU2_SWC2_OP,
CU2_SDC2_OP,
};
extern int register_cu2_notifier(struct notifier_block *nb);
extern int cu2_notifier_call_chain(unsigned long val, void *v);
#endif /* __ASM_COP2_H */

2
arch/mips/include/asm/cpu.h
View File

@ -154,6 +154,8 @@
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
/*
* Older processors used to encode processor version and revision in two

8
arch/mips/include/asm/fpu.h
View File

@ -28,15 +28,7 @@
struct sigcontext;
struct sigcontext32;
extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
extern void fpu_emulator_init_fpu(void);
extern int fpu_emulator_save_context(struct sigcontext __user *sc);
extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
extern void _init_fpu(void);
extern void _save_fp(struct task_struct *);
extern void _restore_fp(struct task_struct *);

24
arch/mips/include/asm/fpu_emulator.h
View File

@ -25,17 +25,27 @@
#include <asm/break.h>
#include <asm/inst.h>
#include <asm/local.h>
#ifdef CONFIG_DEBUG_FS
struct mips_fpu_emulator_stats {
unsigned int emulated;
unsigned int loads;
unsigned int stores;
unsigned int cp1ops;
unsigned int cp1xops;
unsigned int errors;
local_t emulated;
local_t loads;
local_t stores;
local_t cp1ops;
local_t cp1xops;
local_t errors;
};
extern struct mips_fpu_emulator_stats fpuemustats;
DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
#define MIPS_FPU_EMU_INC_STATS(M) \
cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
#else
#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
#endif /* CONFIG_DEBUG_FS */
extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
unsigned long cpc);

91
arch/mips/include/asm/ftrace.h
View File

@ -1 +1,90 @@
/* empty */
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive for
* more details.
*
* Copyright (C) 2009 DSLab, Lanzhou University, China
* Author: Wu Zhangjin <wuzj@lemote.com>
*/
#ifndef _ASM_MIPS_FTRACE_H
#define _ASM_MIPS_FTRACE_H
#ifdef CONFIG_FUNCTION_TRACER
#define MCOUNT_ADDR ((unsigned long)(_mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
#ifndef __ASSEMBLY__
extern void _mcount(void);
#define mcount _mcount
#define safe_load(load, src, dst, error) \
do { \
asm volatile ( \
"1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
" li %[" STR(error) "], 0\n" \
"2:\n" \
\
".section .fixup, \"ax\"\n" \
"3: li %[" STR(error) "], 1\n" \
" j 2b\n" \
".previous\n" \
\
".section\t__ex_table,\"a\"\n\t" \
STR(PTR) "\t1b, 3b\n\t" \
".previous\n" \
\
: [dst] "=&r" (dst), [error] "=r" (error)\
: [src] "r" (src) \
: "memory" \
); \
} while (0)
#define safe_store(store, src, dst, error) \
do { \
asm volatile ( \
"1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
" li %[" STR(error) "], 0\n" \
"2:\n" \
\
".section .fixup, \"ax\"\n" \
"3: li %[" STR(error) "], 1\n" \
" j 2b\n" \
".previous\n" \
\
".section\t__ex_table,\"a\"\n\t"\
STR(PTR) "\t1b, 3b\n\t" \
".previous\n" \
\
: [error] "=r" (error) \
: [dst] "r" (dst), [src] "r" (src)\
: "memory" \
); \
} while (0)
#define safe_load_code(dst, src, error) \
safe_load(STR(lw), src, dst, error)
#define safe_store_code(src, dst, error) \
safe_store(STR(sw), src, dst, error)
#define safe_load_stack(dst, src, error) \
safe_load(STR(PTR_L), src, dst, error)
#define safe_store_stack(src, dst, error) \
safe_store(STR(PTR_S), src, dst, error)
#ifdef CONFIG_DYNAMIC_FTRACE
static inline unsigned long ftrace_call_adjust(unsigned long addr)
{
return addr;
}
struct dyn_arch_ftrace {
};
#endif /* CONFIG_DYNAMIC_FTRACE */
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_FUNCTION_TRACER */
#endif /* _ASM_MIPS_FTRACE_H */

29
arch/mips/include/asm/irq.h
View File

@ -113,36 +113,11 @@ do { \
#endif
/*
* do_IRQ handles all normal device IRQ's (the special
* SMP cross-CPU interrupts have their own specific
* handlers).
*
* Ideally there should be away to get this into kernel/irq/handle.c to
* avoid the overhead of a call for just a tiny function ...
*/
#define do_IRQ(irq) \
do { \
irq_enter(); \
__DO_IRQ_SMTC_HOOK(irq); \
generic_handle_irq(irq); \
irq_exit(); \
} while (0)
extern void do_IRQ(unsigned int irq);
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
/*
* To avoid inefficient and in some cases pathological re-checking of
* IRQ affinity, we have this variant that skips the affinity check.
*/
#define do_IRQ_no_affinity(irq) \
do { \
irq_enter(); \
__NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
generic_handle_irq(irq); \
irq_exit(); \
} while (0)
extern void do_IRQ_no_affinity(unsigned int irq);
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */

48
arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
View File

@ -1,48 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
/*
* Basler eXcite has an RM9122 processor.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */

154
arch/mips/include/asm/mach-excite/excite.h
View File

@ -1,154 +0,0 @@
#ifndef __EXCITE_H__
#define __EXCITE_H__
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#define EXCITE_CPU_EXT_CLOCK 100000000
#if !defined(__ASSEMBLY__)
void __init excite_kgdb_init(void);
void excite_procfs_init(void);
extern unsigned long memsize;
extern char modetty[];
extern u32 unit_id;
#endif
/* Base name for XICAP devices */
#define XICAP_NAME "xicap_gpi"
/* OCD register offsets */
#define LKB0 0x0038
#define LKB5 0x0128
#define LKM5 0x012C
#define LKB7 0x0138
#define LKM7 0x013c
#define LKB8 0x0140
#define LKM8 0x0144
#define LKB9 0x0148
#define LKM9 0x014c
#define LKB10 0x0150
#define LKM10 0x0154
#define LKB11 0x0158
#define LKM11 0x015c
#define LKB12 0x0160
#define LKM12 0x0164
#define LKB13 0x0168
#define LKM13 0x016c
#define LDP0 0x0200
#define LDP1 0x0210
#define LDP2 0x0220
#define LDP3 0x0230
#define INTPIN0 0x0A40
#define INTPIN1 0x0A44
#define INTPIN2 0x0A48
#define INTPIN3 0x0A4C
#define INTPIN4 0x0A50
#define INTPIN5 0x0A54
#define INTPIN6 0x0A58
#define INTPIN7 0x0A5C
/* TITAN register offsets */
#define CPRR 0x0004
#define CPDSR 0x0008
#define CPTC0R 0x000c
#define CPTC1R 0x0010
#define CPCFG0 0x0020
#define CPCFG1 0x0024
#define CPDST0A 0x0028
#define CPDST0B 0x002c
#define CPDST1A 0x0030
#define CPDST1B 0x0034
#define CPXDSTA 0x0038
#define CPXDSTB 0x003c
#define CPXCISRA 0x0048
#define CPXCISRB 0x004c
#define CPGIG0ER 0x0050
#define CPGIG1ER 0x0054
#define CPGRWL 0x0068
#define CPURSLMT 0x00f8
#define UACFG 0x0200
#define UAINTS 0x0204
#define SDRXFCIE 0x4828
#define SDTXFCIE 0x4928
#define INTP0Status0 0x1B00
#define INTP0Mask0 0x1B04
#define INTP0Set0 0x1B08
#define INTP0Clear0 0x1B0C
#define GXCFG 0x5000
#define GXDMADRPFX 0x5018
#define GXDMA_DESCADR 0x501c
#define GXCH0TDESSTRT 0x5054
/* IRQ definitions */
#define NMICONFIG 0xac0
#define TITAN_MSGINT 0xc4
#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
#define FPGA0_MSGINT 0x5a
#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
#define FPGA1_MSGINT 0x7b
#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
#define PHY_MSGINT 0x9c
#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
/* Pre-release units used interrupt pin #9 */
#define USB_IRQ 11
#else
/* Re-designed units use interrupt pin #1 */
#define USB_MSGINT 0x39
#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
#endif
#define TIMER_IRQ 12
/* Device address ranges */
#define EXCITE_OFFS_OCD 0x1fffc000
#define EXCITE_SIZE_OCD (16 * 1024)
#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
#define EXCITE_OFFS_SCRAM 0x1fffa000
#define EXCITE_SIZE_SCRAM (8 << 10)
#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_OFFS_PCI_IO 0x1fff8000
#define EXCITE_SIZE_PCI_IO (8 << 10)
#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_OFFS_TITAN 0x1fff0000
#define EXCITE_SIZE_TITAN (32 << 10)
#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
#define EXCITE_SIZE_PCI_MEM (64 << 10)
#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_OFFS_FPGA 0x1ffdc000
#define EXCITE_SIZE_FPGA (16 << 10)
#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
#define EXCITE_OFFS_NAND 0x1ffd8000
#define EXCITE_SIZE_NAND (16 << 10)
#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
#define EXCITE_OFFS_BOOTROM 0x1f000000
#define EXCITE_SIZE_BOOTROM (8 << 20)
#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
/* FPGA address offsets */
#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
#endif /* __EXCITE_H__ */

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#ifndef EXCITE_FPGA_H_INCLUDED
#define EXCITE_FPGA_H_INCLUDED
/**
* Address alignment of the individual FPGA bytes.
* The address arrangement of the individual bytes of the FPGA is two
* byte aligned at the embedded MK2 platform.
*/
#ifdef EXCITE_CCI_FPGA_MK2
typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
#else
typedef unsigned char excite_cci_fpga_align_t;
#endif
/**
* Size of Dual Ported RAM.
*/
#define EXCITE_DPR_SIZE 263
/**
* Size of Reserved Status Fields in Dual Ported RAM.
*/
#define EXCITE_DPR_STATUS_SIZE 7
/**
* FPGA.
* Hardware register layout of the FPGA interface. The FPGA must accessed
* byte wise solely.
* @see EXCITE_CCI_DPR_MK2
*/
typedef struct excite_fpga {
/**
* Dual Ported RAM.
*/
excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
/**
* Status.
*/
excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
#ifdef EXCITE_CCI_FPGA_MK2
/**
* RM9000 Interrupt.
* Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
*/
excite_cci_fpga_align_t rm9k_int;
#else
/**
* MK2 Interrupt.
* Write access initiates interrupt at the ARM processor of the MK2.
*/
excite_cci_fpga_align_t mk2_int;
excite_cci_fpga_align_t gap[0x1000-0x10f];
/**
* IRQ Source/Acknowledge.
*/
excite_cci_fpga_align_t rm9k_irq_src;
/**
* IRQ Mask.
* Set bits enable the related interrupt.
*/
excite_cci_fpga_align_t rm9k_irq_mask;
#endif
} excite_fpga;
#endif /* ndef EXCITE_FPGA_H_INCLUDED */

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#ifndef __EXCITE_NANDFLASH_H__
#define __EXCITE_NANDFLASH_H__
/* Resource names */
#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
#endif /* __EXCITE_NANDFLASH_H__ */

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#if !defined(__RM9K_ETH_H__)
#define __RM9K_ETH_H__
#define RM9K_GE_NAME "rm9k_ge"
/* Resource names */
#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
#endif /* !defined(__RM9K_ETH_H__) */

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#ifndef __RM9K_WDT_H__
#define __RM9K_WDT_H__
/* Device name */
#define WDT_NAME "wdt_gpi"
/* Resource names */
#define WDT_RESOURCE_REGS "excite_watchdog_regs"
#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
#endif /* __RM9K_WDT_H__ */

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arch/mips/include/asm/mach-excite/rm9k_xicap.h
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#ifndef __EXCITE_XICAP_H__
#define __EXCITE_XICAP_H__
/* Resource names */
#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
#define XICAP_RESOURCE_XDMA "xicap_xdma"
#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
#define XICAP_RESOURCE_IRQ "xicap_irq"
#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
#endif /* __EXCITE_XICAP_H__ */

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/*
* The header file of cs5536 sourth bridge.
*
* Copyright (C) 2007 Lemote, Inc.
* Author : jlliu <liujl@lemote.com>
*/
#ifndef _CS5536_H
#define _CS5536_H
#include <linux/types.h>
extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
extern void _wrmsr(u32 msr, u32 hi, u32 lo);
/*
* MSR module base
*/
#define CS5536_SB_MSR_BASE (0x00000000)
#define CS5536_GLIU_MSR_BASE (0x10000000)
#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
#define CS5536_USB_MSR_BASE (0x40000000)
#define CS5536_IDE_MSR_BASE (0x60000000)
#define CS5536_DIVIL_MSR_BASE (0x80000000)
#define CS5536_ACC_MSR_BASE (0xa0000000)
#define CS5536_UNUSED_MSR_BASE (0xc0000000)
#define CS5536_GLCP_MSR_BASE (0xe0000000)
#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
/*
* BAR SPACE OF VIRTUAL PCI :
* range for pci probe use, length is the actual size.
*/
/* IO space for all DIVIL modules */
#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
#define CS5536_SMB_RANGE 0xfffffff8
#define CS5536_SMB_LENGTH 0x08
#define CS5536_GPIO_RANGE 0xffffff00
#define CS5536_GPIO_LENGTH 0x100
#define CS5536_MFGPT_RANGE 0xffffffc0
#define CS5536_MFGPT_LENGTH 0x40
#define CS5536_ACPI_RANGE 0xffffffe0
#define CS5536_ACPI_LENGTH 0x20
#define CS5536_PMS_RANGE 0xffffff80
#define CS5536_PMS_LENGTH 0x80
/* IO space for IDE */
#define CS5536_IDE_RANGE 0xfffffff0
#define CS5536_IDE_LENGTH 0x10
/* IO space for ACC */
#define CS5536_ACC_RANGE 0xffffff80
#define CS5536_ACC_LENGTH 0x80
/* MEM space for ALL USB modules */
#define CS5536_OHCI_RANGE 0xfffff000
#define CS5536_OHCI_LENGTH 0x1000
#define CS5536_EHCI_RANGE 0xfffff000
#define CS5536_EHCI_LENGTH 0x1000
/*
* PCI MSR ACCESS
*/
#define PCI_MSR_CTRL 0xF0
#define PCI_MSR_ADDR 0xF4
#define PCI_MSR_DATA_LO 0xF8
#define PCI_MSR_DATA_HI 0xFC
/**************** MSR *****************************/
/*
* GLIU STANDARD MSR
*/
#define GLIU_CAP 0x00
#define GLIU_CONFIG 0x01
#define GLIU_SMI 0x02
#define GLIU_ERROR 0x03
#define GLIU_PM 0x04
#define GLIU_DIAG 0x05
/*
* GLIU SPEC. MSR
*/
#define GLIU_P2D_BM0 0x20
#define GLIU_P2D_BM1 0x21
#define GLIU_P2D_BM2 0x22
#define GLIU_P2D_BMK0 0x23
#define GLIU_P2D_BMK1 0x24
#define GLIU_P2D_BM3 0x25
#define GLIU_P2D_BM4 0x26
#define GLIU_COH 0x80
#define GLIU_PAE 0x81
#define GLIU_ARB 0x82
#define GLIU_ASMI 0x83
#define GLIU_AERR 0x84
#define GLIU_DEBUG 0x85
#define GLIU_PHY_CAP 0x86
#define GLIU_NOUT_RESP 0x87
#define GLIU_NOUT_WDATA 0x88
#define GLIU_WHOAMI 0x8B
#define GLIU_SLV_DIS 0x8C
#define GLIU_IOD_BM0 0xE0
#define GLIU_IOD_BM1 0xE1
#define GLIU_IOD_BM2 0xE2
#define GLIU_IOD_BM3 0xE3
#define GLIU_IOD_BM4 0xE4
#define GLIU_IOD_BM5 0xE5
#define GLIU_IOD_BM6 0xE6
#define GLIU_IOD_BM7 0xE7
#define GLIU_IOD_BM8 0xE8
#define GLIU_IOD_BM9 0xE9
#define GLIU_IOD_SC0 0xEA
#define GLIU_IOD_SC1 0xEB
#define GLIU_IOD_SC2 0xEC
#define GLIU_IOD_SC3 0xED
#define GLIU_IOD_SC4 0xEE
#define GLIU_IOD_SC5 0xEF
#define GLIU_IOD_SC6 0xF0
#define GLIU_IOD_SC7 0xF1
/*
* SB STANDARD
*/
#define SB_CAP 0x00
#define SB_CONFIG 0x01
#define SB_SMI 0x02
#define SB_ERROR 0x03
#define SB_MAR_ERR_EN 0x00000001
#define SB_TAR_ERR_EN 0x00000002
#define SB_RSVD_BIT1 0x00000004
#define SB_EXCEP_ERR_EN 0x00000008
#define SB_SYSE_ERR_EN 0x00000010
#define SB_PARE_ERR_EN 0x00000020
#define SB_TAS_ERR_EN 0x00000040
#define SB_MAR_ERR_FLAG 0x00010000
#define SB_TAR_ERR_FLAG 0x00020000
#define SB_RSVD_BIT2 0x00040000
#define SB_EXCEP_ERR_FLAG 0x00080000
#define SB_SYSE_ERR_FLAG 0x00100000
#define SB_PARE_ERR_FLAG 0x00200000
#define SB_TAS_ERR_FLAG 0x00400000
#define SB_PM 0x04
#define SB_DIAG 0x05
/*
* SB SPEC.
*/
#define SB_CTRL 0x10
#define SB_R0 0x20
#define SB_R1 0x21
#define SB_R2 0x22
#define SB_R3 0x23
#define SB_R4 0x24
#define SB_R5 0x25
#define SB_R6 0x26
#define SB_R7 0x27
#define SB_R8 0x28
#define SB_R9 0x29
#define SB_R10 0x2A
#define SB_R11 0x2B
#define SB_R12 0x2C
#define SB_R13 0x2D
#define SB_R14 0x2E
#define SB_R15 0x2F
/*
* GLCP STANDARD
*/
#define GLCP_CAP 0x00
#define GLCP_CONFIG 0x01
#define GLCP_SMI 0x02
#define GLCP_ERROR 0x03
#define GLCP_PM 0x04
#define GLCP_DIAG 0x05
/*
* GLCP SPEC.
*/
#define GLCP_CLK_DIS_DELAY 0x08
#define GLCP_PM_CLK_DISABLE 0x09
#define GLCP_GLB_PM 0x0B
#define GLCP_DBG_OUT 0x0C
#define GLCP_RSVD1 0x0D
#define GLCP_SOFT_COM 0x0E
#define SOFT_BAR_SMB_FLAG 0x00000001
#define SOFT_BAR_GPIO_FLAG 0x00000002
#define SOFT_BAR_MFGPT_FLAG 0x00000004
#define SOFT_BAR_IRQ_FLAG 0x00000008
#define SOFT_BAR_PMS_FLAG 0x00000010
#define SOFT_BAR_ACPI_FLAG 0x00000020
#define SOFT_BAR_IDE_FLAG 0x00000400
#define SOFT_BAR_ACC_FLAG 0x00000800
#define SOFT_BAR_OHCI_FLAG 0x00001000
#define SOFT_BAR_EHCI_FLAG 0x00002000
#define GLCP_RSVD2 0x0F
#define GLCP_CLK_OFF 0x10
#define GLCP_CLK_ACTIVE 0x11
#define GLCP_CLK_DISABLE 0x12
#define GLCP_CLK4ACK 0x13
#define GLCP_SYS_RST 0x14
#define GLCP_RSVD3 0x15
#define GLCP_DBG_CLK_CTRL 0x16
#define GLCP_CHIP_REV_ID 0x17
/* PIC */
#define PIC_YSEL_LOW 0x20
#define PIC_YSEL_LOW_USB_SHIFT 8
#define PIC_YSEL_LOW_ACC_SHIFT 16
#define PIC_YSEL_LOW_FLASH_SHIFT 24
#define PIC_YSEL_HIGH 0x21
#define PIC_ZSEL_LOW 0x22
#define PIC_ZSEL_HIGH 0x23
#define PIC_IRQM_PRIM 0x24
#define PIC_IRQM_LPC 0x25
#define PIC_XIRR_STS_LOW 0x26
#define PIC_XIRR_STS_HIGH 0x27
#define PCI_SHDW 0x34
/*
* DIVIL STANDARD
*/
#define DIVIL_CAP 0x00
#define DIVIL_CONFIG 0x01
#define DIVIL_SMI 0x02
#define DIVIL_ERROR 0x03
#define DIVIL_PM 0x04
#define DIVIL_DIAG 0x05
/*
* DIVIL SPEC.
*/
#define DIVIL_LBAR_IRQ 0x08
#define DIVIL_LBAR_KEL 0x09
#define DIVIL_LBAR_SMB 0x0B
#define DIVIL_LBAR_GPIO 0x0C
#define DIVIL_LBAR_MFGPT 0x0D
#define DIVIL_LBAR_ACPI 0x0E
#define DIVIL_LBAR_PMS 0x0F
#define DIVIL_LEG_IO 0x14
#define DIVIL_BALL_OPTS 0x15
#define DIVIL_SOFT_IRQ 0x16
#define DIVIL_SOFT_RESET 0x17
/* MFGPT */
#define MFGPT_IRQ 0x28
/*
* IDE STANDARD
*/
#define IDE_CAP 0x00
#define IDE_CONFIG 0x01
#define IDE_SMI 0x02
#define IDE_ERROR 0x03
#define IDE_PM 0x04
#define IDE_DIAG 0x05
/*
* IDE SPEC.
*/
#define IDE_IO_BAR 0x08
#define IDE_CFG 0x10
#define IDE_DTC 0x12
#define IDE_CAST 0x13
#define IDE_ETC 0x14
#define IDE_INTERNAL_PM 0x15
/*
* ACC STANDARD
*/
#define ACC_CAP 0x00
#define ACC_CONFIG 0x01
#define ACC_SMI 0x02
#define ACC_ERROR 0x03
#define ACC_PM 0x04
#define ACC_DIAG 0x05
/*
* USB STANDARD
*/
#define USB_CAP 0x00
#define USB_CONFIG 0x01
#define USB_SMI 0x02
#define USB_ERROR 0x03
#define USB_PM 0x04
#define USB_DIAG 0x05
/*
* USB SPEC.
*/
#define USB_OHCI 0x08
#define USB_EHCI 0x09
/****************** NATIVE ***************************/
/* GPIO : I/O SPACE; REG : 32BITS */
#define GPIOL_OUT_VAL 0x00
#define GPIOL_OUT_EN 0x04
#endif /* _CS5536_H */

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/*
* cs5536 mfgpt header file
*/
#ifndef _CS5536_MFGPT_H
#define _CS5536_MFGPT_H
#include <cs5536/cs5536.h>
#include <cs5536/cs5536_pci.h>
#ifdef CONFIG_CS5536_MFGPT
extern void setup_mfgpt0_timer(void);
extern void disable_mfgpt0_counter(void);
extern void enable_mfgpt0_counter(void);
#else
static inline void __maybe_unused setup_mfgpt0_timer(void)
{
}
static inline void __maybe_unused disable_mfgpt0_counter(void)
{
}
static inline void __maybe_unused enable_mfgpt0_counter(void)
{
}
#endif
#define MFGPT_TICK_RATE 14318000
#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
#define MFGPT_BASE mfgpt_base
#define MFGPT0_CMP2 (MFGPT_BASE + 2)
#define MFGPT0_CNT (MFGPT_BASE + 4)
#define MFGPT0_SETUP (MFGPT_BASE + 6)
#endif /*!_CS5536_MFGPT_H */

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arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h Normal file
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/*
* the definition file of cs5536 Virtual Support Module(VSM).
* pci configuration space can be accessed through the VSM, so
* there is no need of the MSR read/write now, except the spec.
* MSR registers which are not implemented yet.
*
* Copyright (C) 2007 Lemote Inc.
* Author : jlliu, liujl@lemote.com
*/
#ifndef _CS5536_PCI_H
#define _CS5536_PCI_H
#include <linux/types.h>
#include <linux/pci_regs.h>
extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
extern u32 cs5536_pci_conf_read4(int function, int reg);
#define CS5536_ACC_INTR 9
#define CS5536_IDE_INTR 14
#define CS5536_USB_INTR 11
#define CS5536_MFGPT_INTR 5
#define CS5536_UART1_INTR 4
#define CS5536_UART2_INTR 3
/************** PCI BUS DEVICE FUNCTION ***************/
/*
* PCI bus device function
*/
#define PCI_BUS_CS5536 0
#define PCI_IDSEL_CS5536 14
/********** STANDARD PCI-2.2 EXPANSION ****************/
/*
* PCI configuration space
* we have to virtualize the PCI configure space head, so we should
* define the necessary IDs and some others.
*/
/* CONFIG of PCI VENDOR ID*/
#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
(((mod_dev_id) << 16) | (sys_vendor_id))
/* VENDOR ID */
#define CS5536_VENDOR_ID 0x1022
/* DEVICE ID */
#define CS5536_ISA_DEVICE_ID 0x2090
#define CS5536_IDE_DEVICE_ID 0x209a
#define CS5536_ACC_DEVICE_ID 0x2093
#define CS5536_OHCI_DEVICE_ID 0x2094
#define CS5536_EHCI_DEVICE_ID 0x2095
/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
#define CS5536_ISA_CLASS_CODE 0x060100
#define CS5536_IDE_CLASS_CODE 0x010180
#define CS5536_ACC_CLASS_CODE 0x040100
#define CS5536_OHCI_CLASS_CODE 0x0C0310
#define CS5536_EHCI_CLASS_CODE 0x0C0320
/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
((PCI_NONE_BIST << 24) | ((header_type) << 16) \
| ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
#define PCI_NORMAL_HEADER_TYPE 0x00
#define PCI_NORMAL_LATENCY_TIMER 0x00
#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
/* BAR */
#define PCI_BAR0_REG 0x10
#define PCI_BAR1_REG 0x14
#define PCI_BAR2_REG 0x18
#define PCI_BAR3_REG 0x1c
#define PCI_BAR4_REG 0x20
#define PCI_BAR5_REG 0x24
#define PCI_BAR_COUNT 6
#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
/* CARDBUS CIS POINTER */
#define PCI_CARDBUS_CIS_POINTER 0x00000000
/* SUBSYSTEM VENDOR ID */
#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
/* SUBSYSTEM ID */
#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
/* EXPANSION ROM BAR */
#define PCI_EXPANSION_ROM_BAR 0x00000000
/* CAPABILITIES POINTER */
#define PCI_CAPLIST_POINTER 0x00000000
#define PCI_CAPLIST_USB_POINTER 0x40
/* INTERRUPT */
#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
((pin) << 8) | (mod_intr))
#define PCI_MAX_LATENCY 0x40
#define PCI_MIN_GRANT 0x00
#define PCI_DEFAULT_PIN 0x01
/*********** EXPANSION PCI REG ************************/
/*
* ISA EXPANSION
*/
#define PCI_UART1_INT_REG 0x50
#define PCI_UART2_INT_REG 0x54
#define PCI_ISA_FIXUP_REG 0x58
/*
* IDE EXPANSION
*/
#define PCI_IDE_CFG_REG 0x40
#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
#define PCI_IDE_DTC_REG 0x48
#define PCI_IDE_CAST_REG 0x4C
#define PCI_IDE_ETC_REG 0x50
#define PCI_IDE_PM_REG 0x54
#define PCI_IDE_INT_REG 0x60
/*
* ACC EXPANSION
*/
#define PCI_ACC_INT_REG 0x50
/*
* OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
*/
#define PCI_OHCI_PM_REG 0x40
#define PCI_OHCI_INT_REG 0x50
/*
* EHCI EXPANSION
*/
#define PCI_EHCI_LEGSMIEN_REG 0x50
#define PCI_EHCI_LEGSMISTS_REG 0x54
#define PCI_EHCI_FLADJ_REG 0x60
#endif /* _CS5536_PCI_H_ */

31
arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h Normal file
View File

@ -0,0 +1,31 @@
/*
* the read/write interfaces for Virtual Support Module(VSM)
*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzj@lemote.com>
*/
#ifndef _CS5536_VSM_H
#define _CS5536_VSM_H
#include <linux/types.h>
typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
typedef u32 (*cs5536_pci_vsm_read)(int reg);
#define DECLARE_CS5536_MODULE(name) \
extern void pci_##name##_write_reg(int reg, u32 value); \
extern u32 pci_##name##_read_reg(int reg);
/* ide module */
DECLARE_CS5536_MODULE(ide)
/* acc module */
DECLARE_CS5536_MODULE(acc)
/* ohci module */
DECLARE_CS5536_MODULE(ohci)
/* isa module */
DECLARE_CS5536_MODULE(isa)
/* ehci module */
DECLARE_CS5536_MODULE(ehci)
#endif /* _CS5536_VSM_H */

4
arch/mips/include/asm/mach-loongson/dma-coherence.h
View File

@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
#else
return dma_addr & 0x7fffffff;
#endif
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,

290
arch/mips/include/asm/mach-loongson/loongson.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzj@lemote.com>
*
* This program is free software; you can redistribute it and/or modify it
@ -15,9 +15,6 @@
#include <linux/io.h>
#include <linux/init.h>
/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
#include <asm/mips-boards/bonito64.h>
/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);
@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_cmdline(void);
extern void __init prom_init_machtype(void);
extern void __init prom_init_env(void);
#ifdef CONFIG_LOONGSON_UART_BASE
extern unsigned long _loongson_uart_base, loongson_uart_base;
extern void prom_init_loongson_uart_base(void);
#endif
static inline void prom_init_uart_base(void)
{
#ifdef CONFIG_LOONGSON_UART_BASE
prom_init_loongson_uart_base();
#endif
}
/* irq operation functions */
extern void bonito_irqdispatch(void);
@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
extern void __init set_irq_trigger_mode(void);
extern void __init mach_init_irq(void);
extern void mach_irq_dispatch(unsigned int pending);
extern int mach_i8259_irq(void);
/* We need this in some places... */
#define delay() ({ \
int x; \
for (x = 0; x < 100000; x++) \
__asm__ __volatile__(""); \
})
#define LOONGSON_REG(x) \
(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
#define LOONGSON_IRQ_BASE 32
#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
#define LOONGSON_FLASH_BASE 0x1c000000
#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
#define LOONGSON_LIO0_BASE 0x1e000000
#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
#define LOONGSON_BOOT_BASE 0x1fc00000
#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
#define LOONGSON_REG_BASE 0x1fe00000
#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
#define LOONGSON_LIO1_BASE 0x1ff00000
#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
#define LOONGSON_PCILO0_BASE 0x10000000
#define LOONGSON_PCILO1_BASE 0x14000000
#define LOONGSON_PCILO2_BASE 0x18000000
#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
#define LOONGSON_PCICFG_BASE 0x1fe80000
#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
#define LOONGSON_PCIIO_BASE 0x1fd00000
#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
/* Loongson Register Bases */
#define LOONGSON_PCICONFIGBASE 0x00
#define LOONGSON_REGBASE 0x100
/* PCI Configuration Registers */
#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c)
#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
#define LOONGSON_PCICMD_PERR_CLR 0x80000000
#define LOONGSON_PCICMD_SERR_CLR 0x40000000
#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
#define LOONGSON_PCICMD_ASTEPEN 0x00000080
#define LOONGSON_PCICMD_SERREN 0x00000100
#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
/* Loongson h/w Configuration */
#define LOONGSON_GENCFG_OFFSET 0x4
#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
#define LOONGSON_GENCFG_SNOOPEN 0x00000002
#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
#define LOONGSON_GENCFG_BYTESWAP 0x00000040
#define LOONGSON_GENCFG_UNCACHED 0x00000080
#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
#define LOONGSON_GENCFG_CACHEALG 0x00000c00
#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
#define LOONGSON_GENCFG_CACHESTOP 0x00002000
#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
#define LOONGSON_GENCFG_BUSERREN 0x00008000
#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
/* PCI address map control */
#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
/* GPIO Regs - r/w */
#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
/* ICU Configuration Regs - r/w */
#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
/* ICU Enable Regs - IntEn & IntISR are r/o. */
#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
/* ICU */
#define LOONGSON_ICU_MBOXES 0x0000000f
#define LOONGSON_ICU_MBOXES_SHIFT 0
#define LOONGSON_ICU_DMARDY 0x00000010
#define LOONGSON_ICU_DMAEMPTY 0x00000020
#define LOONGSON_ICU_COPYRDY 0x00000040
#define LOONGSON_ICU_COPYEMPTY 0x00000080
#define LOONGSON_ICU_COPYERR 0x00000100
#define LOONGSON_ICU_PCIIRQ 0x00000200
#define LOONGSON_ICU_MASTERERR 0x00000400
#define LOONGSON_ICU_SYSTEMERR 0x00000800
#define LOONGSON_ICU_DRAMPERR 0x00001000
#define LOONGSON_ICU_RETRYERR 0x00002000
#define LOONGSON_ICU_GPIOS 0x01ff0000
#define LOONGSON_ICU_GPIOS_SHIFT 16
#define LOONGSON_ICU_GPINS 0x7e000000
#define LOONGSON_ICU_GPINS_SHIFT 25
#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
/* PCI prefetch window base & mask */
#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
/* PCI_Hit*_Sel_* */
#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50)
#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54)
#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58)
#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c)
#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60)
#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64)
#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
/* PXArb Config & Status */
#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68)
#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c)
#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
/* loongson2-specific perf counter IRQ */
#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
/* pcimap */
#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
#include <linux/cpufreq.h>
extern void loongson2_cpu_wait(void);
extern struct cpufreq_frequency_table loongson2_clockmod_table[];
/* Chip Config */
#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
#endif
/*
* address windows configuration module
*
* loongson2e do not have this module
*/
#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
/* address window config module base address */
#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
#define LOONGSON_ADDRWINCFG_SIZE 0x180
extern unsigned long _loongson_addrwincfg_base;
#define LOONGSON_ADDRWINCFG(offset) \
(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
#define ADDRWIN_WIN0 0
#define ADDRWIN_WIN1 1
#define ADDRWIN_WIN2 2
#define ADDRWIN_WIN3 3
#define ADDRWIN_MAP_DST_DDR 0
#define ADDRWIN_MAP_DST_PCI 1
#define ADDRWIN_MAP_DST_LIO 1
/*
* s: CPU, PCIDMA
* d: DDR, PCI, LIO
* win: 0, 1, 2, 3
* src: map source
* dst: map destination
* size: ~mask + 1
*/
#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
s##_WIN##w##_BASE = (src); \
s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
s##_WIN##w##_MASK = ~(size-1); \
} while (0)
#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */

9
arch/mips/include/asm/mach-loongson/machine.h
View File

@ -13,10 +13,15 @@
#ifdef CONFIG_LEMOTE_FULOONG2E
#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
#endif
/* use fuloong2f as the default machine of LEMOTE_MACH2F */
#ifdef CONFIG_LEMOTE_MACH2F
#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
#endif
#endif /* __ASM_MACH_LOONGSON_MACHINE_H */

29
arch/mips/include/asm/mach-loongson/mem.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzj@lemote.com>
*
* This program is free software; you can redistribute it and/or modify it
@ -12,19 +12,30 @@
#define __ASM_MACH_LOONGSON_MEM_H
/*
* On Lemote Loongson 2e
* high memory space
*
* the high memory space starts from 512M.
* the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
* in loongson2e, starts from 512M
* in loongson2f, starts from 2G 256M
*/
#ifdef CONFIG_CPU_LOONGSON2E
#define LOONGSON_HIGHMEM_START 0x20000000
#else
#define LOONGSON_HIGHMEM_START 0x90000000
#endif
/*
* the peripheral registers(MMIO):
*
* On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
* On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
*/
#ifdef CONFIG_LEMOTE_FULOONG2E
#define LOONGSON_HIGHMEM_START 0x20000000
#define LOONGSON_MMIO_MEM_START 0x10000000
#define LOONGSON_MMIO_MEM_END 0x20000000
#ifdef CONFIG_CPU_LOONGSON2E
#define LOONGSON_MMIO_MEM_END 0x20000000
#else
#define LOONGSON_MMIO_MEM_END 0x80000000
#endif
#endif /* __ASM_MACH_LOONGSON_MEM_H */

38
arch/mips/include/asm/mach-loongson/pci.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
* Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
*
* This program is free software; you can redistribute it
* and/or modify it under the terms of the GNU General
@ -22,16 +23,39 @@
#ifndef __ASM_MACH_LOONGSON_PCI_H_
#define __ASM_MACH_LOONGSON_PCI_H_
extern struct pci_ops bonito64_pci_ops;
extern struct pci_ops loongson_pci_ops;
#ifdef CONFIG_LEMOTE_FULOONG2E
/* this pci memory space is mapped by pcimap in pci.c */
#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE
#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2)
/* this is an offset from mips_io_port_base */
#define LOONGSON_PCI_IO_START 0x00004000UL
#endif
#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
/*
* we use address window2 to map cpu address space to pci space
* window2: cpu [1G, 2G] -> pci [1G, 2G]
* why not use window 0 & 1? because they are used by cpu when booting.
* window0: cpu [0, 256M] -> ddr [0, 256M]
* window1: cpu [256M, 512M] -> pci [256M, 512M]
*/
/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
LOONGSON_PCI_MEM_START + 1)
#else /* loongson2f/32bit & loongson2e */
/* this pci memory space is mapped by pcimap in pci.c */
#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
/* this is an offset from mips_io_port_base */
#define LOONGSON_PCI_IO_START 0x00004000UL
#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */

107
arch/mips/include/asm/mach-powertv/asic.h Normal file
View File

@ -0,0 +1,107 @@
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_ASIC_H
#define _ASM_MACH_POWERTV_ASIC_H
#include <linux/ioport.h>
#include <asm/mach-powertv/asic_regs.h>
#define DVR_CAPABLE (1<<0)
#define PCIE_CAPABLE (1<<1)
#define FFS_CAPABLE (1<<2)
#define DISPLAY_CAPABLE (1<<3)
/* Platform Family types
* For compitability, the new value must be added in the end */
enum family_type {
FAMILY_8500,
FAMILY_8500RNG,
FAMILY_4500,
FAMILY_1500,
FAMILY_8600,
FAMILY_4600,
FAMILY_4600VZA,
FAMILY_8600VZB,
FAMILY_1500VZE,
FAMILY_1500VZF,
FAMILIES
};
/* Register maps for each ASIC */
extern const struct register_map calliope_register_map;
extern const struct register_map cronus_register_map;
extern const struct register_map zeus_register_map;
extern struct resource dvr_cronus_resources[];
extern struct resource dvr_zeus_resources[];
extern struct resource non_dvr_calliope_resources[];
extern struct resource non_dvr_cronus_resources[];
extern struct resource non_dvr_cronuslite_resources[];
extern struct resource non_dvr_vz_calliope_resources[];
extern struct resource non_dvr_vze_calliope_resources[];
extern struct resource non_dvr_vzf_calliope_resources[];
extern struct resource non_dvr_zeus_resources[];
extern void powertv_platform_init(void);
extern void platform_alloc_bootmem(void);
extern enum asic_type platform_get_asic(void);
extern enum family_type platform_get_family(void);
extern int platform_supports_dvr(void);
extern int platform_supports_ffs(void);
extern int platform_supports_pcie(void);
extern int platform_supports_display(void);
extern void configure_platform(void);
extern void platform_configure_usb_ehci(void);
extern void platform_unconfigure_usb_ehci(void);
extern void platform_configure_usb_ohci(void);
extern void platform_unconfigure_usb_ohci(void);
/* Platform Resources */
#define ASIC_RESOURCE_GET_EXISTS 1
extern struct resource *asic_resource_get(const char *name);
extern void platform_release_memory(void *baddr, int size);
/* Reboot Cause */
extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
extern void set_locked_reboot_cause(char code, unsigned int data,
unsigned int data2);
enum sys_reboot_type {
sys_unknown_reboot = 0x00, /* Unknown reboot cause */
sys_davic_change = 0x01, /* Reboot due to change in DAVIC
* mode */
sys_user_reboot = 0x02, /* Reboot initiated by user */
sys_system_reboot = 0x03, /* Reboot initiated by OS */
sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
sys_silent_reboot = 0x05, /* Silent reboot */
sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
sys_power_up_reboot = 0x07, /* Power on bootup. Older
* drivers may report as
* userReboot. */
sys_code_change = 0x08, /* Reboot to take code change.
* Older drivers may report as
* userReboot. */
sys_hardware_reset = 0x09, /* HW watchdog or front-panel
* reset button reset. Older
* drivers may report as
* userReboot. */
sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
};
#endif /* _ASM_MACH_POWERTV_ASIC_H */

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/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_MACH_POWERTV_ASIC_H_
#define __ASM_MACH_POWERTV_ASIC_H_
#include <linux/io.h>
/* ASIC types */
enum asic_type {
ASIC_UNKNOWN,
ASIC_ZEUS,
ASIC_CALLIOPE,
ASIC_CRONUS,
ASIC_CRONUSLITE,
ASICS
};
/* hardcoded values read from Chip Version registers */
#define CRONUS_10 0x0B4C1C20
#define CRONUS_11 0x0B4C1C21
#define CRONUSLITE_10 0x0B4C1C40
#define NAND_FLASH_BASE 0x03000000
#define ZEUS_IO_BASE 0x09000000
#define CALLIOPE_IO_BASE 0x08000000
#define CRONUS_IO_BASE 0x09000000
#define ASIC_IO_SIZE 0x01000000
/* Definitions for backward compatibility */
#define UART1_INTSTAT uart1_intstat
#define UART1_INTEN uart1_inten
#define UART1_CONFIG1 uart1_config1
#define UART1_CONFIG2 uart1_config2
#define UART1_DIVISORHI uart1_divisorhi
#define UART1_DIVISORLO uart1_divisorlo
#define UART1_DATA uart1_data
#define UART1_STATUS uart1_status
/* ASIC register enumeration */
struct register_map {
u32 eic_slow0_strt_add;
u32 eic_cfg_bits;
u32 eic_ready_status;
u32 chipver3;
u32 chipver2;
u32 chipver1;
u32 chipver0;
u32 uart1_intstat;
u32 uart1_inten;
u32 uart1_config1;
u32 uart1_config2;
u32 uart1_divisorhi;
u32 uart1_divisorlo;
u32 uart1_data;
u32 uart1_status;
u32 int_stat_3;
u32 int_stat_2;
u32 int_stat_1;
u32 int_stat_0;
u32 int_config;
u32 int_int_scan;
u32 ien_int_3;
u32 ien_int_2;
u32 ien_int_1;
u32 ien_int_0;
u32 int_level_3_3;
u32 int_level_3_2;
u32 int_level_3_1;
u32 int_level_3_0;
u32 int_level_2_3;
u32 int_level_2_2;
u32 int_level_2_1;
u32 int_level_2_0;
u32 int_level_1_3;
u32 int_level_1_2;
u32 int_level_1_1;
u32 int_level_1_0;
u32 int_level_0_3;
u32 int_level_0_2;
u32 int_level_0_1;
u32 int_level_0_0;
u32 int_docsis_en;
u32 mips_pll_setup;
u32 usb_fs;
u32 test_bus;
u32 crt_spare;
u32 usb2_ohci_int_mask;
u32 usb2_strap;
u32 ehci_hcapbase;
u32 ohci_hc_revision;
u32 bcm1_bs_lmi_steer;
u32 usb2_control;
u32 usb2_stbus_obc;
u32 usb2_stbus_mess_size;
u32 usb2_stbus_chunk_size;
u32 pcie_regs;
u32 tim_ch;
u32 tim_cl;
u32 gpio_dout;
u32 gpio_din;
u32 gpio_dir;
u32 watchdog;
u32 front_panel;
u32 register_maps;
};
extern enum asic_type asic;
extern const struct register_map *register_map;
extern unsigned long asic_phy_base; /* Physical address of ASIC */
extern unsigned long asic_base; /* Virtual address of ASIC */
/*
* Macros to interface to registers through their ioremapped address
* asic_reg_offset Returns the offset of a given register from the start
* of the ASIC address space
* asic_reg_phys_addr Returns the physical address of the given register
* asic_reg_addr Returns the iomapped virtual address of the given
* register.
*/
#define asic_reg_offset(x) (register_map->x)
#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
#define asic_reg_addr(x) \
((unsigned int *) (asic_base + asic_reg_offset(x)))
/*
* The asic_reg macro is gone. It should be replaced by either asic_read or
* asic_write, as appropriate.
*/
#define asic_read(x) readl(asic_reg_addr(x))
#define asic_write(v, x) writel(v, asic_reg_addr(x))
extern void asic_irq_init(void);
#endif

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