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perf/x86: Implement 64-bit counter support for IBS
This patch implements 64 bit counter support for IBS. The sampling period is no longer limited to the hw counter width. The functions perf_event_set_period() and perf_event_try_update() can be used as generic functions. They can replace similar code that is duplicate across architectures. Signed-off-by: Robert Richter <robert.richter@amd.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1323968199-9326-5-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Robert Richter
Ingo Molnar
parent
4db2e8e650
commit
db98c5faf8
@ -177,6 +177,8 @@ struct x86_pmu_capability {
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* IbsOpCtl bits */
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/* lower 4 bits of the current count are ignored: */
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#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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@ -44,9 +44,11 @@ struct perf_ibs {
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u64 cnt_mask;
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u64 enable_mask;
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u64 valid_mask;
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u64 max_period;
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unsigned long offset_mask[1];
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int offset_max;
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struct cpu_perf_ibs __percpu *pcpu;
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u64 (*get_count)(u64 config);
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};
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struct perf_ibs_data {
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@ -58,6 +60,78 @@ struct perf_ibs_data {
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u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
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};
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static int
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perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *count)
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{
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int overflow = 0;
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/*
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* If we are way outside a reasonable range then just skip forward:
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*/
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left < min))
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left = min;
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if (left > max)
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left = max;
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*count = (u64)left;
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return overflow;
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}
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static int
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perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
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{
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struct hw_perf_event *hwc = &event->hw;
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int shift = 64 - width;
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u64 prev_raw_count;
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u64 delta;
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/*
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* Careful: an NMI might modify the previous event value.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic event atomically:
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*/
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prev_raw_count = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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return 0;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (event-)time and add that to the generic event.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count.
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*/
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return 1;
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}
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static struct perf_ibs perf_ibs_fetch;
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static struct perf_ibs perf_ibs_op;
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@ -91,18 +165,14 @@ static int perf_ibs_init(struct perf_event *event)
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if (hwc->sample_period & 0x0f)
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/* lower 4 bits can not be set in ibs max cnt */
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return -EINVAL;
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max_cnt = hwc->sample_period >> 4;
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if (max_cnt & ~perf_ibs->cnt_mask)
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/* out of range */
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return -EINVAL;
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config |= max_cnt;
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} else {
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max_cnt = config & perf_ibs->cnt_mask;
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config &= ~perf_ibs->cnt_mask;
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event->attr.sample_period = max_cnt << 4;
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hwc->sample_period = event->attr.sample_period;
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}
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if (!max_cnt)
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if (!hwc->sample_period)
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return -EINVAL;
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hwc->config_base = perf_ibs->msr;
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@ -111,16 +181,71 @@ static int perf_ibs_init(struct perf_event *event)
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return 0;
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}
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static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
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struct hw_perf_event *hwc, u64 *period)
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{
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int ret;
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/* ignore lower 4 bits in min count: */
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ret = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
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local64_set(&hwc->prev_count, 0);
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return ret;
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}
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static u64 get_ibs_fetch_count(u64 config)
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{
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return (config & IBS_FETCH_CNT) >> 12;
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}
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static u64 get_ibs_op_count(u64 config)
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{
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return (config & IBS_OP_CUR_CNT) >> 32;
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}
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static void
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perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
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u64 config)
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{
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u64 count = perf_ibs->get_count(config);
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while (!perf_event_try_update(event, count, 20)) {
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rdmsrl(event->hw.config_base, config);
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count = perf_ibs->get_count(config);
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}
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}
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/* Note: The enable mask must be encoded in the config argument. */
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static inline void perf_ibs_enable_event(struct hw_perf_event *hwc, u64 config)
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{
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wrmsrl(hwc->config_base, hwc->config | config);
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}
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/*
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* We cannot restore the ibs pmu state, so we always needs to update
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* the event while stopping it and then reset the state when starting
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* again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
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* perf_ibs_start()/perf_ibs_stop() and instead always do it.
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*/
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static void perf_ibs_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 config;
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if (test_and_set_bit(IBS_STARTED, pcpu->state))
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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wrmsrl(hwc->config_base, hwc->config | perf_ibs->enable_mask);
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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perf_ibs_set_period(perf_ibs, hwc, &config);
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config = (config >> 4) | perf_ibs->enable_mask;
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set_bit(IBS_STARTED, pcpu->state);
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perf_ibs_enable_event(hwc, config);
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perf_event_update_userpage(event);
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}
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static void perf_ibs_stop(struct perf_event *event, int flags)
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@ -129,15 +254,28 @@ static void perf_ibs_stop(struct perf_event *event, int flags)
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 val;
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int stopping;
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if (!test_and_clear_bit(IBS_STARTED, pcpu->state))
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stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
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if (!stopping && (hwc->state & PERF_HES_UPTODATE))
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return;
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set_bit(IBS_STOPPING, pcpu->state);
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rdmsrl(hwc->config_base, val);
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val &= ~perf_ibs->enable_mask;
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wrmsrl(hwc->config_base, val);
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if (stopping) {
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set_bit(IBS_STOPPING, pcpu->state);
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val &= ~perf_ibs->enable_mask;
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wrmsrl(hwc->config_base, val);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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}
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_ibs_event_update(perf_ibs, event, val);
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hwc->state |= PERF_HES_UPTODATE;
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}
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static int perf_ibs_add(struct perf_event *event, int flags)
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@ -148,6 +286,8 @@ static int perf_ibs_add(struct perf_event *event, int flags)
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if (test_and_set_bit(IBS_ENABLED, pcpu->state))
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return -ENOSPC;
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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pcpu->event = event;
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if (flags & PERF_EF_START)
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@ -164,9 +304,11 @@ static void perf_ibs_del(struct perf_event *event, int flags)
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if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
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return;
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perf_ibs_stop(event, 0);
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perf_ibs_stop(event, PERF_EF_UPDATE);
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pcpu->event = NULL;
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perf_event_update_userpage(event);
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}
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static void perf_ibs_read(struct perf_event *event) { }
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@ -187,8 +329,11 @@ static struct perf_ibs perf_ibs_fetch = {
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.cnt_mask = IBS_FETCH_MAX_CNT,
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.enable_mask = IBS_FETCH_ENABLE,
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.valid_mask = IBS_FETCH_VAL,
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.max_period = IBS_FETCH_MAX_CNT << 4,
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.offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
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.offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
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.get_count = get_ibs_fetch_count,
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};
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static struct perf_ibs perf_ibs_op = {
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@ -207,8 +352,11 @@ static struct perf_ibs perf_ibs_op = {
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.cnt_mask = IBS_OP_MAX_CNT,
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.enable_mask = IBS_OP_ENABLE,
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.valid_mask = IBS_OP_VAL,
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.max_period = IBS_OP_MAX_CNT << 4,
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.offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
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.offset_max = MSR_AMD64_IBSOP_REG_COUNT,
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.get_count = get_ibs_op_count,
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};
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static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
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@ -220,9 +368,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
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struct perf_raw_record raw;
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struct pt_regs regs;
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struct perf_ibs_data ibs_data;
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int offset, size;
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int offset, size, overflow, reenable;
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unsigned int msr;
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u64 *buf;
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u64 *buf, config;
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if (!test_bit(IBS_STARTED, pcpu->state)) {
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/* Catch spurious interrupts after stopping IBS: */
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@ -257,11 +405,25 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
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regs = *iregs; /* XXX: update ip from ibs sample */
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if (perf_event_overflow(event, &data, ®s))
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; /* stop */
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else
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/* reenable */
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wrmsrl(hwc->config_base, hwc->config | perf_ibs->enable_mask);
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/*
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* Emulate IbsOpCurCnt in MSRC001_1033 (IbsOpCtl), not
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* supported in all cpus. As this triggered an interrupt, we
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* set the current count to the max count.
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*/
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config = ibs_data.regs[0];
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if (perf_ibs == &perf_ibs_op && !(ibs_caps & IBS_CAPS_RDWROPCNT)) {
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config &= ~IBS_OP_CUR_CNT;
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config |= (config & IBS_OP_MAX_CNT) << 36;
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}
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perf_ibs_event_update(perf_ibs, event, config);
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overflow = perf_ibs_set_period(perf_ibs, hwc, &config);
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reenable = !(overflow && perf_event_overflow(event, &data, ®s));
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config = (config >> 4) | (reenable ? perf_ibs->enable_mask : 0);
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perf_ibs_enable_event(hwc, config);
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perf_event_update_userpage(event);
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return 1;
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}
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