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net: lan966x: add the basic lan966x driver

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This patch adds basic SwitchDev driver framework for lan966x. It
includes only the IO range mapping and probing of the switch.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Horatiu Vultur 2021-11-29 13:43:55 +01:00 committed by David S. Miller
parent 642fcf53a9
commit db8bcaad53
7 changed files with 1207 additions and 0 deletions
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1
drivers/net/ethernet/microchip/Kconfig
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@ -55,6 +55,7 @@ config LAN743X
To compile this driver as a module, choose M here. The module will be
called lan743x.
source "drivers/net/ethernet/microchip/lan966x/Kconfig"
source "drivers/net/ethernet/microchip/sparx5/Kconfig"
endif # NET_VENDOR_MICROCHIP

1
drivers/net/ethernet/microchip/Makefile
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@ -9,4 +9,5 @@ obj-$(CONFIG_LAN743X) += lan743x.o
lan743x-objs := lan743x_main.o lan743x_ethtool.o lan743x_ptp.o
obj-$(CONFIG_LAN966X_SWITCH) += lan966x/
obj-$(CONFIG_SPARX5_SWITCH) += sparx5/

7
drivers/net/ethernet/microchip/lan966x/Kconfig Normal file
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@ -0,0 +1,7 @@
config LAN966X_SWITCH
tristate "Lan966x switch driver"
depends on HAS_IOMEM
depends on OF
select PHYLINK
help
This driver supports the Lan966x network switch device.

8
drivers/net/ethernet/microchip/lan966x/Makefile Normal file
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@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for the Microchip Lan966x network device drivers.
#
obj-$(CONFIG_LAN966X_SWITCH) += lan966x-switch.o
lan966x-switch-objs := lan966x_main.o

357
drivers/net/ethernet/microchip/lan966x/lan966x_main.c Normal file
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@ -0,0 +1,357 @@
// SPDX-License-Identifier: GPL-2.0+
#include <linux/module.h>
#include <linux/if_bridge.h>
#include <linux/iopoll.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/reset.h>
#include "lan966x_main.h"
#define READL_SLEEP_US 10
#define READL_TIMEOUT_US 100000000
#define IO_RANGES 2
static const struct of_device_id lan966x_match[] = {
{ .compatible = "microchip,lan966x-switch" },
{ }
};
MODULE_DEVICE_TABLE(of, lan966x_match);
struct lan966x_main_io_resource {
enum lan966x_target id;
phys_addr_t offset;
int range;
};
static const struct lan966x_main_io_resource lan966x_main_iomap[] = {
{ TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
{ TARGET_ORG, 0, 1 }, /* 0xe2000000 */
{ TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */
{ TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */
{ TARGET_CHIP_TOP, 0x10000, 1 }, /* 0xe2010000 */
{ TARGET_REW, 0x14000, 1 }, /* 0xe2014000 */
{ TARGET_SYS, 0x28000, 1 }, /* 0xe2028000 */
{ TARGET_DEV, 0x34000, 1 }, /* 0xe2034000 */
{ TARGET_DEV + 1, 0x38000, 1 }, /* 0xe2038000 */
{ TARGET_DEV + 2, 0x3c000, 1 }, /* 0xe203c000 */
{ TARGET_DEV + 3, 0x40000, 1 }, /* 0xe2040000 */
{ TARGET_DEV + 4, 0x44000, 1 }, /* 0xe2044000 */
{ TARGET_DEV + 5, 0x48000, 1 }, /* 0xe2048000 */
{ TARGET_DEV + 6, 0x4c000, 1 }, /* 0xe204c000 */
{ TARGET_DEV + 7, 0x50000, 1 }, /* 0xe2050000 */
{ TARGET_QSYS, 0x100000, 1 }, /* 0xe2100000 */
{ TARGET_AFI, 0x120000, 1 }, /* 0xe2120000 */
{ TARGET_ANA, 0x140000, 1 }, /* 0xe2140000 */
};
static int lan966x_create_targets(struct platform_device *pdev,
struct lan966x *lan966x)
{
struct resource *iores[IO_RANGES];
void __iomem *begin[IO_RANGES];
int idx;
/* Initially map the entire range and after that update each target to
* point inside the region at the correct offset. It is possible that
* other devices access the same region so don't add any checks about
* this.
*/
for (idx = 0; idx < IO_RANGES; idx++) {
iores[idx] = platform_get_resource(pdev, IORESOURCE_MEM,
idx);
if (!iores[idx]) {
dev_err(&pdev->dev, "Invalid resource\n");
return -EINVAL;
}
begin[idx] = devm_ioremap(&pdev->dev,
iores[idx]->start,
resource_size(iores[idx]));
if (IS_ERR(begin[idx])) {
dev_err(&pdev->dev, "Unable to get registers: %s\n",
iores[idx]->name);
return PTR_ERR(begin[idx]);
}
}
for (idx = 0; idx < ARRAY_SIZE(lan966x_main_iomap); idx++) {
const struct lan966x_main_io_resource *iomap =
&lan966x_main_iomap[idx];
lan966x->regs[iomap->id] = begin[iomap->range] + iomap->offset;
}
return 0;
}
static int lan966x_probe_port(struct lan966x *lan966x, u32 p,
phy_interface_t phy_mode)
{
struct lan966x_port *port;
if (p >= lan966x->num_phys_ports)
return -EINVAL;
port = devm_kzalloc(lan966x->dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
port->lan966x = lan966x;
port->chip_port = p;
port->pvid = PORT_PVID;
lan966x->ports[p] = port;
return 0;
}
static void lan966x_init(struct lan966x *lan966x)
{
u32 p, i;
/* Flush queues */
lan_wr(lan_rd(lan966x, QS_XTR_FLUSH) |
GENMASK(1, 0),
lan966x, QS_XTR_FLUSH);
/* Allow to drain */
mdelay(1);
/* All Queues normal */
lan_wr(lan_rd(lan966x, QS_XTR_FLUSH) &
~(GENMASK(1, 0)),
lan966x, QS_XTR_FLUSH);
/* Set MAC age time to default value, the entry is aged after
* 2 * AGE_PERIOD
*/
lan_wr(ANA_AUTOAGE_AGE_PERIOD_SET(BR_DEFAULT_AGEING_TIME / 2 / HZ),
lan966x, ANA_AUTOAGE);
/* Disable learning for frames discarded by VLAN ingress filtering */
lan_rmw(ANA_ADVLEARN_VLAN_CHK_SET(1),
ANA_ADVLEARN_VLAN_CHK,
lan966x, ANA_ADVLEARN);
/* Setup frame ageing - "2 sec" - The unit is 6.5 us on lan966x */
lan_wr(SYS_FRM_AGING_AGE_TX_ENA_SET(1) |
(20000000 / 65),
lan966x, SYS_FRM_AGING);
/* Map the 8 CPU extraction queues to CPU port */
lan_wr(0, lan966x, QSYS_CPU_GROUP_MAP);
/* Do byte-swap and expect status after last data word
* Extraction: Mode: manual extraction) | Byte_swap
*/
lan_wr(QS_XTR_GRP_CFG_MODE_SET(1) |
QS_XTR_GRP_CFG_BYTE_SWAP_SET(1),
lan966x, QS_XTR_GRP_CFG(0));
/* Injection: Mode: manual injection | Byte_swap */
lan_wr(QS_INJ_GRP_CFG_MODE_SET(1) |
QS_INJ_GRP_CFG_BYTE_SWAP_SET(1),
lan966x, QS_INJ_GRP_CFG(0));
lan_rmw(QS_INJ_CTRL_GAP_SIZE_SET(0),
QS_INJ_CTRL_GAP_SIZE,
lan966x, QS_INJ_CTRL(0));
/* Enable IFH insertion/parsing on CPU ports */
lan_wr(SYS_PORT_MODE_INCL_INJ_HDR_SET(1) |
SYS_PORT_MODE_INCL_XTR_HDR_SET(1),
lan966x, SYS_PORT_MODE(CPU_PORT));
/* Setup flooding PGIDs */
lan_wr(ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(PGID_MCIPV4) |
ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(PGID_MC) |
ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(PGID_MC) |
ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(PGID_MC),
lan966x, ANA_FLOODING_IPMC);
/* There are 8 priorities */
for (i = 0; i < 8; ++i)
lan_rmw(ANA_FLOODING_FLD_MULTICAST_SET(PGID_MC) |
ANA_FLOODING_FLD_BROADCAST_SET(PGID_BC),
ANA_FLOODING_FLD_MULTICAST |
ANA_FLOODING_FLD_BROADCAST,
lan966x, ANA_FLOODING(i));
for (i = 0; i < PGID_ENTRIES; ++i)
/* Set all the entries to obey VLAN_VLAN */
lan_rmw(ANA_PGID_CFG_OBEY_VLAN_SET(1),
ANA_PGID_CFG_OBEY_VLAN,
lan966x, ANA_PGID_CFG(i));
for (p = 0; p < lan966x->num_phys_ports; p++) {
/* Disable bridging by default */
lan_rmw(ANA_PGID_PGID_SET(0x0),
ANA_PGID_PGID,
lan966x, ANA_PGID(p + PGID_SRC));
/* Do not forward BPDU frames to the front ports and copy them
* to CPU
*/
lan_wr(0xffff, lan966x, ANA_CPU_FWD_BPDU_CFG(p));
}
/* Set source buffer size for each priority and each port to 1500 bytes */
for (i = 0; i <= QSYS_Q_RSRV; ++i) {
lan_wr(1500 / 64, lan966x, QSYS_RES_CFG(i));
lan_wr(1500 / 64, lan966x, QSYS_RES_CFG(512 + i));
}
/* Enable switching to/from cpu port */
lan_wr(QSYS_SW_PORT_MODE_PORT_ENA_SET(1) |
QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(1) |
QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(1),
lan966x, QSYS_SW_PORT_MODE(CPU_PORT));
/* Configure and enable the CPU port */
lan_rmw(ANA_PGID_PGID_SET(0),
ANA_PGID_PGID,
lan966x, ANA_PGID(CPU_PORT));
lan_rmw(ANA_PGID_PGID_SET(BIT(CPU_PORT)),
ANA_PGID_PGID,
lan966x, ANA_PGID(PGID_CPU));
/* Multicast to all other ports */
lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),
ANA_PGID_PGID,
lan966x, ANA_PGID(PGID_MC));
/* This will be controlled by mrouter ports */
lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),
ANA_PGID_PGID,
lan966x, ANA_PGID(PGID_MCIPV4));
/* Broadcast to the CPU port and to other ports */
lan_rmw(ANA_PGID_PGID_SET(BIT(CPU_PORT) | GENMASK(lan966x->num_phys_ports - 1, 0)),
ANA_PGID_PGID,
lan966x, ANA_PGID(PGID_BC));
lan_wr(REW_PORT_CFG_NO_REWRITE_SET(1),
lan966x, REW_PORT_CFG(CPU_PORT));
lan_rmw(ANA_ANAINTR_INTR_ENA_SET(1),
ANA_ANAINTR_INTR_ENA,
lan966x, ANA_ANAINTR);
}
static int lan966x_ram_init(struct lan966x *lan966x)
{
return lan_rd(lan966x, SYS_RAM_INIT);
}
static int lan966x_reset_switch(struct lan966x *lan966x)
{
struct reset_control *switch_reset, *phy_reset;
int val = 0;
int ret;
switch_reset = devm_reset_control_get_shared(lan966x->dev, "switch");
if (IS_ERR(switch_reset))
return dev_err_probe(lan966x->dev, PTR_ERR(switch_reset),
"Could not obtain switch reset");
phy_reset = devm_reset_control_get_shared(lan966x->dev, "phy");
if (IS_ERR(phy_reset))
return dev_err_probe(lan966x->dev, PTR_ERR(phy_reset),
"Could not obtain phy reset\n");
reset_control_reset(switch_reset);
reset_control_reset(phy_reset);
lan_wr(SYS_RESET_CFG_CORE_ENA_SET(0), lan966x, SYS_RESET_CFG);
lan_wr(SYS_RAM_INIT_RAM_INIT_SET(1), lan966x, SYS_RAM_INIT);
ret = readx_poll_timeout(lan966x_ram_init, lan966x,
val, (val & BIT(1)) == 0, READL_SLEEP_US,
READL_TIMEOUT_US);
if (ret)
return ret;
lan_wr(SYS_RESET_CFG_CORE_ENA_SET(1), lan966x, SYS_RESET_CFG);
return 0;
}
static int lan966x_probe(struct platform_device *pdev)
{
struct fwnode_handle *ports, *portnp;
struct lan966x *lan966x;
int err, i;
lan966x = devm_kzalloc(&pdev->dev, sizeof(*lan966x), GFP_KERNEL);
if (!lan966x)
return -ENOMEM;
platform_set_drvdata(pdev, lan966x);
lan966x->dev = &pdev->dev;
ports = device_get_named_child_node(&pdev->dev, "ethernet-ports");
if (!ports)
return dev_err_probe(&pdev->dev, -ENODEV,
"no ethernet-ports child found\n");
err = lan966x_create_targets(pdev, lan966x);
if (err)
return dev_err_probe(&pdev->dev, err,
"Failed to create targets");
err = lan966x_reset_switch(lan966x);
if (err)
return dev_err_probe(&pdev->dev, err, "Reset failed");
i = 0;
fwnode_for_each_available_child_node(ports, portnp)
++i;
lan966x->num_phys_ports = i;
lan966x->ports = devm_kcalloc(&pdev->dev, lan966x->num_phys_ports,
sizeof(struct lan966x_port *),
GFP_KERNEL);
if (!lan966x->ports)
return -ENOMEM;
/* There QS system has 32KB of memory */
lan966x->shared_queue_sz = LAN966X_BUFFER_MEMORY;
/* init switch */
lan966x_init(lan966x);
/* go over the child nodes */
fwnode_for_each_available_child_node(ports, portnp) {
phy_interface_t phy_mode;
u32 p;
if (fwnode_property_read_u32(portnp, "reg", &p))
continue;
phy_mode = fwnode_get_phy_mode(portnp);
err = lan966x_probe_port(lan966x, p, phy_mode);
if (err)
goto cleanup_ports;
}
return 0;
cleanup_ports:
fwnode_handle_put(portnp);
return err;
}
static struct platform_driver lan966x_driver = {
.probe = lan966x_probe,
.driver = {
.name = "lan966x-switch",
.of_match_table = lan966x_match,
},
};
module_platform_driver(lan966x_driver);
MODULE_DESCRIPTION("Microchip LAN966X switch driver");
MODULE_AUTHOR("Horatiu Vultur <horatiu.vultur@microchip.com>");
MODULE_LICENSE("Dual MIT/GPL");

103
drivers/net/ethernet/microchip/lan966x/lan966x_main.h Normal file
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@ -0,0 +1,103 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __LAN966X_MAIN_H__
#define __LAN966X_MAIN_H__
#include "lan966x_regs.h"
#define LAN966X_BUFFER_CELL_SZ 64
#define LAN966X_BUFFER_MEMORY (160 * 1024)
#define LAN966X_BUFFER_MIN_SZ 60
#define PGID_AGGR 64
#define PGID_SRC 80
#define PGID_ENTRIES 89
#define PORT_PVID 0
/* Reserved amount for (SRC, PRIO) at index 8*SRC + PRIO */
#define QSYS_Q_RSRV 95
/* Reserved PGIDs */
#define PGID_CPU (PGID_AGGR - 6)
#define PGID_UC (PGID_AGGR - 5)
#define PGID_BC (PGID_AGGR - 4)
#define PGID_MC (PGID_AGGR - 3)
#define PGID_MCIPV4 (PGID_AGGR - 2)
#define PGID_MCIPV6 (PGID_AGGR - 1)
#define LAN966X_SPEED_NONE 0
#define LAN966X_SPEED_1000 1
#define LAN966X_SPEED_100 2
#define LAN966X_SPEED_10 3
#define CPU_PORT 8
struct lan966x_port;
struct lan966x {
struct device *dev;
u8 num_phys_ports;
struct lan966x_port **ports;
void __iomem *regs[NUM_TARGETS];
int shared_queue_sz;
};
struct lan966x_port {
struct lan966x *lan966x;
u8 chip_port;
u16 pvid;
};
static inline void __iomem *lan_addr(void __iomem *base[],
int id, int tinst, int tcnt,
int gbase, int ginst,
int gcnt, int gwidth,
int raddr, int rinst,
int rcnt, int rwidth)
{
WARN_ON((tinst) >= tcnt);
WARN_ON((ginst) >= gcnt);
WARN_ON((rinst) >= rcnt);
return base[id + (tinst)] +
gbase + ((ginst) * gwidth) +
raddr + ((rinst) * rwidth);
}
static inline u32 lan_rd(struct lan966x *lan966x, int id, int tinst, int tcnt,
int gbase, int ginst, int gcnt, int gwidth,
int raddr, int rinst, int rcnt, int rwidth)
{
return readl(lan_addr(lan966x->regs, id, tinst, tcnt, gbase, ginst,
gcnt, gwidth, raddr, rinst, rcnt, rwidth));
}
static inline void lan_wr(u32 val, struct lan966x *lan966x,
int id, int tinst, int tcnt,
int gbase, int ginst, int gcnt, int gwidth,
int raddr, int rinst, int rcnt, int rwidth)
{
writel(val, lan_addr(lan966x->regs, id, tinst, tcnt,
gbase, ginst, gcnt, gwidth,
raddr, rinst, rcnt, rwidth));
}
static inline void lan_rmw(u32 val, u32 mask, struct lan966x *lan966x,
int id, int tinst, int tcnt,
int gbase, int ginst, int gcnt, int gwidth,
int raddr, int rinst, int rcnt, int rwidth)
{
u32 nval;
nval = readl(lan_addr(lan966x->regs, id, tinst, tcnt, gbase, ginst,
gcnt, gwidth, raddr, rinst, rcnt, rwidth));
nval = (nval & ~mask) | (val & mask);
writel(nval, lan_addr(lan966x->regs, id, tinst, tcnt, gbase, ginst,
gcnt, gwidth, raddr, rinst, rcnt, rwidth));
}
#endif /* __LAN966X_MAIN_H__ */

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drivers/net/ethernet/microchip/lan966x/lan966x_regs.h Normal file
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@ -0,0 +1,730 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
* Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty)
*/
#ifndef _LAN966X_REGS_H_
#define _LAN966X_REGS_H_
#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>
enum lan966x_target {
TARGET_AFI = 2,
TARGET_ANA = 3,
TARGET_CHIP_TOP = 5,
TARGET_CPU = 6,
TARGET_DEV = 13,
TARGET_GCB = 27,
TARGET_ORG = 36,
TARGET_QS = 42,
TARGET_QSYS = 46,
TARGET_REW = 47,
TARGET_SYS = 52,
NUM_TARGETS = 66
};
#define __REG(...) __VA_ARGS__
/* AFI:PORT_TBL:PORT_FRM_OUT */
#define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)
#define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16)
#define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\
FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
#define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\
FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
/* AFI:PORT_TBL:PORT_CFG */
#define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)
#define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16)
#define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\
FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
#define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\
FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
#define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0)
#define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\
FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
#define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\
FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x)
/* ANA:ANA:ADVLEARN */
#define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4)
#define ANA_ADVLEARN_VLAN_CHK BIT(0)
#define ANA_ADVLEARN_VLAN_CHK_SET(x)\
FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
#define ANA_ADVLEARN_VLAN_CHK_GET(x)\
FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x)
/* ANA:ANA:ANAINTR */
#define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4)
#define ANA_ANAINTR_INTR BIT(1)
#define ANA_ANAINTR_INTR_SET(x)\
FIELD_PREP(ANA_ANAINTR_INTR, x)
#define ANA_ANAINTR_INTR_GET(x)\
FIELD_GET(ANA_ANAINTR_INTR, x)
#define ANA_ANAINTR_INTR_ENA BIT(0)
#define ANA_ANAINTR_INTR_ENA_SET(x)\
FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
#define ANA_ANAINTR_INTR_ENA_GET(x)\
FIELD_GET(ANA_ANAINTR_INTR_ENA, x)
/* ANA:ANA:AUTOAGE */
#define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4)
#define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1)
#define ANA_AUTOAGE_AGE_PERIOD_SET(x)\
FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
#define ANA_AUTOAGE_AGE_PERIOD_GET(x)\
FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x)
/* ANA:ANA:FLOODING */
#define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4)
#define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6)
#define ANA_FLOODING_FLD_BROADCAST_SET(x)\
FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x)
#define ANA_FLOODING_FLD_BROADCAST_GET(x)\
FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x)
#define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0)
#define ANA_FLOODING_FLD_MULTICAST_SET(x)\
FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x)
#define ANA_FLOODING_FLD_MULTICAST_GET(x)\
FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x)
/* ANA:ANA:FLOODING_IPMC */
#define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\
FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\
FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\
FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\
FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\
FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\
FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\
FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\
FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
/* ANA:PGID:PGID */
#define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4)
#define ANA_PGID_PGID GENMASK(8, 0)
#define ANA_PGID_PGID_SET(x)\
FIELD_PREP(ANA_PGID_PGID, x)
#define ANA_PGID_PGID_GET(x)\
FIELD_GET(ANA_PGID_PGID, x)
/* ANA:PGID:PGID_CFG */
#define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4)
#define ANA_PGID_CFG_OBEY_VLAN BIT(0)
#define ANA_PGID_CFG_OBEY_VLAN_SET(x)\
FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x)
#define ANA_PGID_CFG_OBEY_VLAN_GET(x)\
FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x)
/* ANA:ANA_TABLES:MACHDATA */
#define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)
/* ANA:ANA_TABLES:MACLDATA */
#define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4)
/* ANA:ANA_TABLES:MACACCESS */
#define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4)
#define ANA_MACACCESS_CHANGE2SW BIT(17)
#define ANA_MACACCESS_CHANGE2SW_SET(x)\
FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x)
#define ANA_MACACCESS_CHANGE2SW_GET(x)\
FIELD_GET(ANA_MACACCESS_CHANGE2SW, x)
#define ANA_MACACCESS_VALID BIT(12)
#define ANA_MACACCESS_VALID_SET(x)\
FIELD_PREP(ANA_MACACCESS_VALID, x)
#define ANA_MACACCESS_VALID_GET(x)\
FIELD_GET(ANA_MACACCESS_VALID, x)
#define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10)
#define ANA_MACACCESS_ENTRYTYPE_SET(x)\
FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x)
#define ANA_MACACCESS_ENTRYTYPE_GET(x)\
FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x)
#define ANA_MACACCESS_DEST_IDX GENMASK(9, 4)
#define ANA_MACACCESS_DEST_IDX_SET(x)\
FIELD_PREP(ANA_MACACCESS_DEST_IDX, x)
#define ANA_MACACCESS_DEST_IDX_GET(x)\
FIELD_GET(ANA_MACACCESS_DEST_IDX, x)
#define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0)
#define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\
FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x)
#define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\
FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x)
/* ANA:PORT:CPU_FWD_CFG */
#define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)
#define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3)
#define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\
FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
#define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\
FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
/* ANA:PORT:CPU_FWD_BPDU_CFG */
#define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4)
/* ANA:PORT:PORT_CFG */
#define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4)
#define ANA_PORT_CFG_LEARNAUTO BIT(6)
#define ANA_PORT_CFG_LEARNAUTO_SET(x)\
FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x)
#define ANA_PORT_CFG_LEARNAUTO_GET(x)\
FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x)
#define ANA_PORT_CFG_LEARN_ENA BIT(5)
#define ANA_PORT_CFG_LEARN_ENA_SET(x)\
FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x)
#define ANA_PORT_CFG_LEARN_ENA_GET(x)\
FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x)
#define ANA_PORT_CFG_RECV_ENA BIT(4)
#define ANA_PORT_CFG_RECV_ENA_SET(x)\
FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x)
#define ANA_PORT_CFG_RECV_ENA_GET(x)\
FIELD_GET(ANA_PORT_CFG_RECV_ENA, x)
#define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0)
#define ANA_PORT_CFG_PORTID_VAL_SET(x)\
FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x)
#define ANA_PORT_CFG_PORTID_VAL_GET(x)\
FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)
/* ANA:PFC:PFC_CFG */
#define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4)
#define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0)
#define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\
FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x)
#define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\
FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)
/* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */
#define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4)
#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0)
#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\
FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\
FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
/* DEV:PORT_MODE:CLOCK_CFG */
#define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4)
#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
#define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x)
#define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x)
#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
#define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x)
#define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x)
#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
#define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x)
#define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x)
#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
#define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x)
#define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x)
#define DEV_CLOCK_CFG_PORT_RST BIT(3)
#define DEV_CLOCK_CFG_PORT_RST_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x)
#define DEV_CLOCK_CFG_PORT_RST_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x)
#define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0)
#define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\
FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x)
#define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\
FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x)
/* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */
#define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4)
#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
#define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\
FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x)
#define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\
FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x)
#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
#define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\
FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x)
#define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\
FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x)
/* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */
#define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
/* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
#define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4)
#define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
#define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
#define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
/* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */
#define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4)
#define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
#define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\
FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x)
#define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\
FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x)
#define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
#define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\
FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x)
#define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\
FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x)
#define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
#define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\
FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x)
#define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\
FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x)
/* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */
#define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4)
#define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16)
#define DEV_MAC_HDX_CFG_SEED_SET(x)\
FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x)
#define DEV_MAC_HDX_CFG_SEED_GET(x)\
FIELD_GET(DEV_MAC_HDX_CFG_SEED, x)
#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
#define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\
FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x)
#define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\
FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x)
/* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */
#define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4)
/* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */
#define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4)
/* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */
#define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4)
#define DEV_PCS1G_CFG_PCS_ENA BIT(0)
#define DEV_PCS1G_CFG_PCS_ENA_SET(x)\
FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x)
#define DEV_PCS1G_CFG_PCS_ENA_GET(x)\
FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
#define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4)
#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
#define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4)
#define DEV_PCS1G_SD_CFG_SD_ENA BIT(0)
#define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\
FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x)
#define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\
FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
#define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4)
#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)
#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1)
#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
#define DEV_PCS1G_ANEG_CFG_ENA BIT(0)
#define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x)
#define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
#define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4)
#define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16)
#define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
#define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
#define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4)
#define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
#define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
#define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
/* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */
#define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4)
#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
/* DEVCPU_QS:XTR:XTR_GRP_CFG */
#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)
#define QS_XTR_GRP_CFG_MODE_SET(x)\
FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
#define QS_XTR_GRP_CFG_MODE_GET(x)\
FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
#define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
#define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
/* DEVCPU_QS:XTR:XTR_RD */
#define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
/* DEVCPU_QS:XTR:XTR_FLUSH */
#define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */
#define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
/* DEVCPU_QS:INJ:INJ_GRP_CFG */
#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)
#define QS_INJ_GRP_CFG_MODE_SET(x)\
FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
#define QS_INJ_GRP_CFG_MODE_GET(x)\
FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
#define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
#define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
/* DEVCPU_QS:INJ:INJ_WR */
#define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
/* DEVCPU_QS:INJ:INJ_CTRL */
#define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
#define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)
#define QS_INJ_CTRL_GAP_SIZE_SET(x)\
FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
#define QS_INJ_CTRL_GAP_SIZE_GET(x)\
FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
#define QS_INJ_CTRL_EOF BIT(19)
#define QS_INJ_CTRL_EOF_SET(x)\
FIELD_PREP(QS_INJ_CTRL_EOF, x)
#define QS_INJ_CTRL_EOF_GET(x)\
FIELD_GET(QS_INJ_CTRL_EOF, x)
#define QS_INJ_CTRL_SOF BIT(18)
#define QS_INJ_CTRL_SOF_SET(x)\
FIELD_PREP(QS_INJ_CTRL_SOF, x)
#define QS_INJ_CTRL_SOF_GET(x)\
FIELD_GET(QS_INJ_CTRL_SOF, x)
#define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)
#define QS_INJ_CTRL_VLD_BYTES_SET(x)\
FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
#define QS_INJ_CTRL_VLD_BYTES_GET(x)\
FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
/* DEVCPU_QS:INJ:INJ_STATUS */
#define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
#define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)
#define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
#define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
#define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)
#define QS_INJ_STATUS_FIFO_RDY_SET(x)\
FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
#define QS_INJ_STATUS_FIFO_RDY_GET(x)\
FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
/* QSYS:SYSTEM:PORT_MODE */
#define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4)
#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
#define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\
FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x)
#define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\
FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x)
/* QSYS:SYSTEM:SWITCH_PORT_MODE */
#define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4)
#define QSYS_SW_PORT_MODE_PORT_ENA BIT(18)
#define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\
FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x)
#define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\
FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x)
#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14)
#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\
FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\
FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12)
#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
#define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4)
#define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\
FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
#define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\
FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
#define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0)
#define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\
FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x)
#define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\
FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x)
/* QSYS:SYSTEM:SW_STATUS */
#define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4)
#define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0)
#define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\
FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x)
#define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\
FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x)
/* QSYS:SYSTEM:CPU_GROUP_MAP */
#define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4)
/* QSYS:RES_CTRL:RES_CFG */
#define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)
/* REW:PORT:PORT_CFG */
#define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4)
#define REW_PORT_CFG_NO_REWRITE BIT(0)
#define REW_PORT_CFG_NO_REWRITE_SET(x)\
FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x)
#define REW_PORT_CFG_NO_REWRITE_GET(x)\
FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)
/* SYS:SYSTEM:RESET_CFG */
#define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4)
#define SYS_RESET_CFG_CORE_ENA BIT(0)
#define SYS_RESET_CFG_CORE_ENA_SET(x)\
FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x)
#define SYS_RESET_CFG_CORE_ENA_GET(x)\
FIELD_GET(SYS_RESET_CFG_CORE_ENA, x)
/* SYS:SYSTEM:PORT_MODE */
#define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4)
#define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4)
#define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\
FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x)
#define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\
FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x)
#define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2)
#define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\
FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x)
#define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\
FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x)
/* SYS:SYSTEM:FRONT_PORT_MODE */
#define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4)
#define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1)
#define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\
FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x)
#define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\
FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x)
/* SYS:SYSTEM:FRM_AGING */
#define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4)
#define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
#define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\
FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x)
#define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\
FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x)
/* SYS:SYSTEM:STAT_CFG */
#define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4)
#define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0)
#define SYS_STAT_CFG_STAT_VIEW_SET(x)\
FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x)
#define SYS_STAT_CFG_STAT_VIEW_GET(x)\
FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x)
/* SYS:PAUSE_CFG:PAUSE_CFG */
#define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4)
#define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10)
#define SYS_PAUSE_CFG_PAUSE_START_SET(x)\
FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x)
#define SYS_PAUSE_CFG_PAUSE_START_GET(x)\
FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x)
#define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1)
#define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x)
#define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x)
#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
#define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x)
#define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x)
/* SYS:PAUSE_CFG:ATOP */
#define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4)
/* SYS:PAUSE_CFG:ATOP_TOT_CFG */
#define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4)
/* SYS:PAUSE_CFG:MAC_FC_CFG */
#define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
#define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
#define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x)
#define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x)
#define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
#define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x)
#define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\
FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\
FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
/* SYS:STAT:CNT */
#define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4)
/* SYS:RAM_CTRL:RAM_INIT */
#define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4)
#define SYS_RAM_INIT_RAM_INIT BIT(1)
#define SYS_RAM_INIT_RAM_INIT_SET(x)\
FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x)
#define SYS_RAM_INIT_RAM_INIT_GET(x)\
FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)
#endif /* _LAN966X_REGS_H_ */