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s2io: Making LRO and UFO as module loadable parameter.
This patch adds two load parameters napi and ufo. Previously NAPI was compilation option with these changes wan enable disable NAPI using load parameter. Also we are introducing ufo load parameter to enable/disable ufo feature Signed-off-by: Sivakumar Subramani <sivakumar.subramani@neterion.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
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7517c1b787
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db874e65ae
@ -401,9 +401,10 @@ S2IO_PARM_INT(lro, 0);
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* aggregation happens until we hit max IP pkt size(64K)
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*/
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S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
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#ifndef CONFIG_S2IO_NAPI
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S2IO_PARM_INT(indicate_max_pkts, 0);
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#endif
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S2IO_PARM_INT(napi, 1);
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S2IO_PARM_INT(ufo, 0);
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static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
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{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
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@ -2274,9 +2275,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
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struct config_param *config;
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u64 tmp;
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buffAdd_t *ba;
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#ifndef CONFIG_S2IO_NAPI
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unsigned long flags;
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#endif
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RxD_t *first_rxdp = NULL;
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mac_control = &nic->mac_control;
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@ -2320,12 +2319,15 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
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DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
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dev->name, rxdp);
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}
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#ifndef CONFIG_S2IO_NAPI
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spin_lock_irqsave(&nic->put_lock, flags);
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mac_control->rings[ring_no].put_pos =
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(block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
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spin_unlock_irqrestore(&nic->put_lock, flags);
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#endif
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if(!napi) {
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spin_lock_irqsave(&nic->put_lock, flags);
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mac_control->rings[ring_no].put_pos =
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(block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
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spin_unlock_irqrestore(&nic->put_lock, flags);
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} else {
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mac_control->rings[ring_no].put_pos =
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(block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
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}
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if ((rxdp->Control_1 & RXD_OWN_XENA) &&
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((nic->rxd_mode >= RXD_MODE_3A) &&
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(rxdp->Control_2 & BIT(0)))) {
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@ -2568,7 +2570,6 @@ static void free_rx_buffers(struct s2io_nic *sp)
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* 0 on success and 1 if there are No Rx packets to be processed.
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*/
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#if defined(CONFIG_S2IO_NAPI)
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static int s2io_poll(struct net_device *dev, int *budget)
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{
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nic_t *nic = dev->priv;
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@ -2633,7 +2634,6 @@ no_rx:
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atomic_dec(&nic->isr_cnt);
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return 1;
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}
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#endif
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#ifdef CONFIG_NET_POLL_CONTROLLER
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/**
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@ -2707,9 +2707,7 @@ static void rx_intr_handler(ring_info_t *ring_data)
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rx_curr_get_info_t get_info, put_info;
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RxD_t *rxdp;
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struct sk_buff *skb;
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#ifndef CONFIG_S2IO_NAPI
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int pkt_cnt = 0;
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#endif
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int i;
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spin_lock(&nic->rx_lock);
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@ -2725,16 +2723,18 @@ static void rx_intr_handler(ring_info_t *ring_data)
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put_info = ring_data->rx_curr_put_info;
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put_block = put_info.block_index;
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rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
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#ifndef CONFIG_S2IO_NAPI
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spin_lock(&nic->put_lock);
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put_offset = ring_data->put_pos;
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spin_unlock(&nic->put_lock);
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#else
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put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
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put_info.offset;
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#endif
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if (!napi) {
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spin_lock(&nic->put_lock);
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put_offset = ring_data->put_pos;
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spin_unlock(&nic->put_lock);
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} else
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put_offset = ring_data->put_pos;
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while (RXD_IS_UP2DT(rxdp)) {
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/* If your are next to put index then it's FIFO full condition */
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/*
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* If your are next to put index then it's
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* FIFO full condition
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*/
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if ((get_block == put_block) &&
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(get_info.offset + 1) == put_info.offset) {
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DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
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@ -2792,15 +2792,12 @@ static void rx_intr_handler(ring_info_t *ring_data)
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rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
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}
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#ifdef CONFIG_S2IO_NAPI
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nic->pkts_to_process -= 1;
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if (!nic->pkts_to_process)
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if ((napi) && (!nic->pkts_to_process))
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break;
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#else
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pkt_cnt++;
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if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
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break;
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#endif
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}
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if (nic->lro) {
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/* Clear all LRO sessions before exiting */
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@ -4193,26 +4190,26 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
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org_mask = readq(&bar0->general_int_mask);
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writeq(val64, &bar0->general_int_mask);
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#ifdef CONFIG_S2IO_NAPI
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if (reason & GEN_INTR_RXTRAFFIC) {
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if (netif_rx_schedule_prep(dev)) {
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writeq(val64, &bar0->rx_traffic_mask);
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__netif_rx_schedule(dev);
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if (napi) {
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if (reason & GEN_INTR_RXTRAFFIC) {
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if (netif_rx_schedule_prep(dev)) {
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writeq(val64, &bar0->rx_traffic_mask);
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__netif_rx_schedule(dev);
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}
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}
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} else {
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/*
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* Rx handler is called by default, without checking for the
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* cause of interrupt.
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* rx_traffic_int reg is an R1 register, writing all 1's
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* will ensure that the actual interrupt causing bit get's
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* cleared and hence a read can be avoided.
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*/
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writeq(val64, &bar0->rx_traffic_int);
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for (i = 0; i < config->rx_ring_num; i++) {
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rx_intr_handler(&mac_control->rings[i]);
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}
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}
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#else
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/*
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* Rx handler is called by default, without checking for the
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* cause of interrupt.
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* rx_traffic_int reg is an R1 register, writing all 1's
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* will ensure that the actual interrupt causing bit get's
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* cleared and hence a read can be avoided.
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*/
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writeq(val64, &bar0->rx_traffic_int);
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for (i = 0; i < config->rx_ring_num; i++) {
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rx_intr_handler(&mac_control->rings[i]);
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}
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#endif
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/*
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* tx_traffic_int reg is an R1 register, writing all 1's
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@ -4231,11 +4228,14 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
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* reallocate the buffers from the interrupt handler itself,
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* else schedule a tasklet to reallocate the buffers.
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*/
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#ifndef CONFIG_S2IO_NAPI
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for (i = 0; i < config->rx_ring_num; i++)
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s2io_chk_rx_buffers(sp, i);
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#endif
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writeq(org_mask, &bar0->general_int_mask);
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if (!napi) {
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for (i = 0; i < config->rx_ring_num; i++)
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s2io_chk_rx_buffers(sp, i);
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}
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writeq(0, &bar0->general_int_mask);
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readl(&bar0->general_int_status);
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atomic_dec(&sp->isr_cnt);
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return IRQ_HANDLED;
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}
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@ -6578,23 +6578,20 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
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if (!sp->lro) {
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skb->protocol = eth_type_trans(skb, dev);
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#ifdef CONFIG_S2IO_NAPI
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if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
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/* Queueing the vlan frame to the upper layer */
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vlan_hwaccel_receive_skb(skb, sp->vlgrp,
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RXD_GET_VLAN_TAG(rxdp->Control_2));
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if (napi)
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vlan_hwaccel_receive_skb(skb, sp->vlgrp,
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RXD_GET_VLAN_TAG(rxdp->Control_2));
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else
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vlan_hwaccel_rx(skb, sp->vlgrp,
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RXD_GET_VLAN_TAG(rxdp->Control_2));
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} else {
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netif_receive_skb(skb);
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if (napi)
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netif_receive_skb(skb);
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else
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netif_rx(skb);
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}
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#else
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if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
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/* Queueing the vlan frame to the upper layer */
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vlan_hwaccel_rx(skb, sp->vlgrp,
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RXD_GET_VLAN_TAG(rxdp->Control_2));
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} else {
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netif_rx(skb);
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}
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#endif
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} else {
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send_up:
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queue_rx_frame(skb);
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@ -6695,13 +6692,9 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
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DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
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rx_ring_num = 8;
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}
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#ifdef CONFIG_S2IO_NAPI
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if (*dev_intr_type != INTA) {
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DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
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"MSI/MSI-X is enabled. Defaulting to INTA\n");
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*dev_intr_type = INTA;
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}
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#endif
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if (*dev_intr_type != INTA)
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napi = 0;
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#ifndef CONFIG_PCI_MSI
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if (*dev_intr_type != INTA) {
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DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
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@ -6962,10 +6955,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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* will use eth_mac_addr() for dev->set_mac_address
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* mac address will be set every time dev->open() is called
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*/
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#if defined(CONFIG_S2IO_NAPI)
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dev->poll = s2io_poll;
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dev->weight = 32;
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#endif
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#ifdef CONFIG_NET_POLL_CONTROLLER
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dev->poll_controller = s2io_netpoll;
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@ -6976,7 +6967,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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dev->features |= NETIF_F_HIGHDMA;
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dev->features |= NETIF_F_TSO;
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dev->features |= NETIF_F_TSO6;
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if (sp->device_type & XFRAME_II_DEVICE) {
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if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
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dev->features |= NETIF_F_UFO;
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dev->features |= NETIF_F_HW_CSUM;
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}
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@ -7057,9 +7048,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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/* Initialize spinlocks */
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spin_lock_init(&sp->tx_lock);
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#ifndef CONFIG_S2IO_NAPI
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spin_lock_init(&sp->put_lock);
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#endif
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if (!napi)
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spin_lock_init(&sp->put_lock);
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spin_lock_init(&sp->rx_lock);
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/*
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@ -7120,9 +7111,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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dev->name);
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break;
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}
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#ifdef CONFIG_S2IO_NAPI
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DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
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#endif
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if (napi)
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DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
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switch(sp->intr_type) {
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case INTA:
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DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
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@ -7137,7 +7128,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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if (sp->lro)
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DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
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dev->name);
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if (ufo)
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DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
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" enabled\n", dev->name);
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/* Initialize device name */
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sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
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@ -7539,11 +7532,10 @@ static void queue_rx_frame(struct sk_buff *skb)
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struct net_device *dev = skb->dev;
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skb->protocol = eth_type_trans(skb, dev);
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#ifdef CONFIG_S2IO_NAPI
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netif_receive_skb(skb);
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#else
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netif_rx(skb);
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#endif
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if (napi)
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netif_receive_skb(skb);
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else
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netif_rx(skb);
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}
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static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
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@ -616,10 +616,8 @@ typedef struct ring_info {
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*/
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rx_curr_get_info_t rx_curr_get_info;
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#ifndef CONFIG_S2IO_NAPI
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/* Index to the absolute position of the put pointer of Rx ring */
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int put_pos;
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#endif
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/* Buffer Address store. */
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buffAdd_t **ba;
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@ -738,13 +736,11 @@ typedef struct lro {
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/* Structure representing one instance of the NIC */
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struct s2io_nic {
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int rxd_mode;
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#ifdef CONFIG_S2IO_NAPI
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/*
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* Count of packets to be processed in a given iteration, it will be indicated
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* by the quota field of the device structure when NAPI is enabled.
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*/
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int pkts_to_process;
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#endif
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struct net_device *dev;
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mac_info_t mac_control;
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struct config_param config;
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@ -775,9 +771,7 @@ struct s2io_nic {
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atomic_t rx_bufs_left[MAX_RX_RINGS];
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spinlock_t tx_lock;
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#ifndef CONFIG_S2IO_NAPI
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spinlock_t put_lock;
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#endif
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#define PROMISC 1
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#define ALL_MULTI 2
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@ -985,9 +979,7 @@ static void s2io_tasklet(unsigned long dev_addr);
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static void s2io_set_multicast(struct net_device *dev);
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static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
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static void s2io_link(nic_t * sp, int link);
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#if defined(CONFIG_S2IO_NAPI)
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static int s2io_poll(struct net_device *dev, int *budget);
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#endif
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static void s2io_init_pci(nic_t * sp);
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static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
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static void s2io_alarm_handle(unsigned long data);
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