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clk: stm32f4: Add lcd-tft clock
This patch introduces lcd-tft clock for stm32f4 soc. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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517633ef63
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@ -51,6 +51,8 @@
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#define NONE -1
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#define NONE -1
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#define NO_IDX NONE
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#define NO_IDX NONE
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#define NO_MUX NONE
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#define NO_GATE NONE
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struct stm32f4_gate_data {
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struct stm32f4_gate_data {
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u8 offset;
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u8 offset;
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@ -942,11 +944,37 @@ static const char *rtc_parents[4] = {
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"no-clock", "lse", "lsi", "hse-rtc"
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"no-clock", "lse", "lsi", "hse-rtc"
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};
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};
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static const char *lcd_parent[1] = { "pllsai-r-div" };
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struct stm32_aux_clk {
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int idx;
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const char *name;
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const char * const *parent_names;
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int num_parents;
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int offset_mux;
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u8 shift;
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u8 mask;
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int offset_gate;
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u8 bit_idx;
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unsigned long flags;
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};
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struct stm32f4_clk_data {
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struct stm32f4_clk_data {
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const struct stm32f4_gate_data *gates_data;
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const struct stm32f4_gate_data *gates_data;
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const u64 *gates_map;
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const u64 *gates_map;
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int gates_num;
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int gates_num;
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const struct stm32f4_pll_data *pll_data;
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const struct stm32f4_pll_data *pll_data;
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const struct stm32_aux_clk *aux_clk;
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int aux_clk_num;
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};
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static const struct stm32_aux_clk stm32f429_aux_clk[] = {
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{
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CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
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NO_MUX, 0, 0,
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STM32F4_RCC_APB2ENR, 26,
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CLK_SET_RATE_PARENT
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},
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};
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};
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static const struct stm32f4_clk_data stm32f429_clk_data = {
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static const struct stm32f4_clk_data stm32f429_clk_data = {
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@ -954,6 +982,8 @@ static const struct stm32f4_clk_data stm32f429_clk_data = {
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.gates_map = stm32f42xx_gate_map,
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.gates_map = stm32f42xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f429_gates),
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.gates_num = ARRAY_SIZE(stm32f429_gates),
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.pll_data = stm32f429_pll,
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.pll_data = stm32f429_pll,
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.aux_clk = stm32f429_aux_clk,
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.aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
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};
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};
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static const struct stm32f4_clk_data stm32f469_clk_data = {
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static const struct stm32f4_clk_data stm32f469_clk_data = {
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@ -961,6 +991,8 @@ static const struct stm32f4_clk_data stm32f469_clk_data = {
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.gates_map = stm32f46xx_gate_map,
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.gates_map = stm32f46xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f469_gates),
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.gates_num = ARRAY_SIZE(stm32f469_gates),
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.pll_data = stm32f469_pll,
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.pll_data = stm32f469_pll,
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.aux_clk = stm32f429_aux_clk,
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.aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
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};
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};
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static const struct of_device_id stm32f4_of_match[] = {
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static const struct of_device_id stm32f4_of_match[] = {
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@ -975,6 +1007,66 @@ static const struct of_device_id stm32f4_of_match[] = {
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{}
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{}
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};
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};
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static struct clk_hw *stm32_register_aux_clk(const char *name,
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const char * const *parent_names, int num_parents,
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int offset_mux, u8 shift, u8 mask,
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int offset_gate, u8 bit_idx,
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unsigned long flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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struct clk_gate *gate;
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struct clk_mux *mux = NULL;
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struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
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const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
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if (offset_gate != NO_GATE) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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hw = ERR_PTR(-EINVAL);
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goto fail;
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}
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gate->reg = base + offset_gate;
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gate->bit_idx = bit_idx;
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gate->flags = 0;
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gate->lock = lock;
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gate_hw = &gate->hw;
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gate_ops = &clk_gate_ops;
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}
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if (offset_mux != NO_MUX) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux) {
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kfree(gate);
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hw = ERR_PTR(-EINVAL);
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goto fail;
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}
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mux->reg = base + offset_mux;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = 0;
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mux_hw = &mux->hw;
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mux_ops = &clk_mux_ops;
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}
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if (mux_hw == NULL && gate_hw == NULL)
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return ERR_PTR(-EINVAL);
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, mux_ops,
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NULL, NULL,
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gate_hw, gate_ops,
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flags);
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if (IS_ERR(hw)) {
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kfree(gate);
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kfree(mux);
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}
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fail:
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return hw;
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}
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static void __init stm32f4_rcc_init(struct device_node *np)
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static void __init stm32f4_rcc_init(struct device_node *np)
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{
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{
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const char *hse_clk;
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const char *hse_clk;
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@ -1134,6 +1226,28 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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goto fail;
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goto fail;
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}
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}
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for (n = 0; n < data->aux_clk_num; n++) {
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const struct stm32_aux_clk *aux_clk;
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struct clk_hw *hw;
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aux_clk = &data->aux_clk[n];
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hw = stm32_register_aux_clk(aux_clk->name,
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aux_clk->parent_names, aux_clk->num_parents,
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aux_clk->offset_mux, aux_clk->shift,
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aux_clk->mask, aux_clk->offset_gate,
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aux_clk->bit_idx, aux_clk->flags,
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&stm32f4_clk_lock);
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if (IS_ERR(hw)) {
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pr_warn("Unable to register %s clk\n", aux_clk->name);
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continue;
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}
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if (aux_clk->idx != NO_IDX)
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clks[aux_clk->idx] = hw;
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}
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of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
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of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
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return;
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return;
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fail:
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fail:
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