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spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers
This extends the driver with support for all SPI framesizes from 4 to 16 bits, and adds support for per transfer specific bits_per_word, while at the same time reducing code size and complexity. Signed-off-by: Esben Haabendal <eha@deif.com> Acked-by: Martin Hundebøll <martin@geanix.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Esben Haabendal
Mark Brown
parent
0a4ec2c158
commit
dadcf4abd6
@ -38,8 +38,6 @@
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#define DRIVER_NAME "fsl-dspi"
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#define TRAN_STATE_WORD_ODD_NUM 0x04
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#define DSPI_FIFO_SIZE 4
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#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
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@ -187,13 +185,13 @@ struct fsl_dspi {
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struct spi_message *cur_msg;
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struct chip_data *cur_chip;
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size_t len;
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void *tx;
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void *tx_end;
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const void *tx;
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void *rx;
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void *rx_end;
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char dataflags;
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u16 void_write_data;
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u16 tx_cmd;
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u8 bits_per_word;
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u8 bytes_per_word;
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const struct fsl_dspi_devtype_data *devtype_data;
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wait_queue_head_t waitq;
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@ -202,15 +200,43 @@ struct fsl_dspi {
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struct fsl_dspi_dma *dma;
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};
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static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word);
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static inline int is_double_byte_mode(struct fsl_dspi *dspi)
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static u16 dspi_pop_tx(struct fsl_dspi *dspi)
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{
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unsigned int val;
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u16 txdata = 0;
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regmap_read(dspi->regmap, SPI_CTAR(0), &val);
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if (dspi->tx) {
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if (dspi->bytes_per_word == 1)
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txdata = *(u8 *)dspi->tx;
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else /* dspi->bytes_per_word == 2 */
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txdata = *(u16 *)dspi->tx;
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dspi->tx += dspi->bytes_per_word;
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}
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dspi->len -= dspi->bytes_per_word;
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return txdata;
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}
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return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
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static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
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{
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u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
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if (dspi->len > 0)
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cmd |= SPI_PUSHR_CMD_CONT;
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return cmd << 16 | data;
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}
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static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
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{
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if (!dspi->rx)
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return;
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/* Mask of undefined bits */
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rxdata &= (1 << dspi->bits_per_word) - 1;
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if (dspi->bytes_per_word == 1)
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*(u8 *)dspi->rx = rxdata;
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else /* dspi->bytes_per_word == 2 */
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*(u16 *)dspi->rx = rxdata;
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dspi->rx += dspi->bytes_per_word;
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}
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static void dspi_tx_dma_callback(void *arg)
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@ -225,19 +251,11 @@ static void dspi_rx_dma_callback(void *arg)
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{
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struct fsl_dspi *dspi = arg;
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struct fsl_dspi_dma *dma = dspi->dma;
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int rx_word;
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int i;
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u16 d;
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rx_word = is_double_byte_mode(dspi);
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if (dspi->rx) {
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for (i = 0; i < dma->curr_xfer_len; i++) {
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d = dspi->dma->rx_dma_buf[i];
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rx_word ? (*(u16 *)dspi->rx = d) :
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(*(u8 *)dspi->rx = d);
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dspi->rx += rx_word + 1;
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}
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for (i = 0; i < dma->curr_xfer_len; i++)
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dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
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}
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complete(&dma->cmd_rx_complete);
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@ -248,14 +266,10 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
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struct fsl_dspi_dma *dma = dspi->dma;
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struct device *dev = &dspi->pdev->dev;
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int time_left;
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int tx_word;
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int i;
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tx_word = is_double_byte_mode(dspi);
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for (i = 0; i < dma->curr_xfer_len; i++) {
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dspi->dma->tx_dma_buf[i] = dspi_data_to_pushr(dspi, tx_word);
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}
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for (i = 0; i < dma->curr_xfer_len; i++)
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dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
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dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
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dma->tx_dma_phys,
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@ -326,16 +340,14 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi)
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struct device *dev = &dspi->pdev->dev;
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int curr_remaining_bytes;
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int bytes_per_buffer;
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int word = 1;
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int ret = 0;
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if (is_double_byte_mode(dspi))
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word = 2;
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curr_remaining_bytes = dspi->len;
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bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
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while (curr_remaining_bytes) {
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/* Check if current transfer fits the DMA buffer */
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dma->curr_xfer_len = curr_remaining_bytes / word;
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dma->curr_xfer_len = curr_remaining_bytes
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/ dspi->bytes_per_word;
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if (dma->curr_xfer_len > bytes_per_buffer)
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dma->curr_xfer_len = bytes_per_buffer;
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@ -345,7 +357,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi)
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goto exit;
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} else {
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curr_remaining_bytes -= dma->curr_xfer_len * word;
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curr_remaining_bytes -= dma->curr_xfer_len
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* dspi->bytes_per_word;
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if (curr_remaining_bytes < 0)
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curr_remaining_bytes = 0;
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}
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@ -531,127 +544,56 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns,
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}
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}
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static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
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static void fifo_write(struct fsl_dspi *dspi)
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{
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u16 data, cmd;
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if (dspi->tx) {
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data = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
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dspi->tx += tx_word + 1;
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} else {
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data = dspi->void_write_data;
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}
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dspi->len -= tx_word + 1;
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cmd = dspi->tx_cmd;
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if (dspi->len > 0)
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cmd |= SPI_PUSHR_CMD_CONT;
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return (cmd << 16) | SPI_PUSHR_TXDATA(data);
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
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}
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static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
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static void dspi_tcfq_write(struct fsl_dspi *dspi)
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{
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u16 d;
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unsigned int val;
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regmap_read(dspi->regmap, SPI_POPR, &val);
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d = SPI_POPR_RXDATA(val);
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if (dspi->rx) {
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rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
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dspi->rx += rx_word + 1;
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}
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/* Clear transfer count */
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dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
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/* Write one entry to both TX FIFO and CMD FIFO simultaneously */
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fifo_write(dspi);
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}
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static int dspi_eoq_write(struct fsl_dspi *dspi)
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static u32 fifo_read(struct fsl_dspi *dspi)
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{
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int tx_count = 0;
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int tx_word;
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u32 dspi_pushr = 0;
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u32 rxdata = 0;
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tx_word = is_double_byte_mode(dspi);
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while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
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/* If we are in word mode, only have a single byte to transfer
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* switch to byte mode temporarily. Will switch back at the
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* end of the transfer.
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*/
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if (tx_word && (dspi->len == 1)) {
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
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regmap_update_bits(dspi->regmap, SPI_CTAR(0),
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SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
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tx_word = 0;
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}
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dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
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if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1)
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/* request EOQ flag for last transfer in queue */
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dspi_pushr |= SPI_PUSHR_EOQ;
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/* Clear transfer counter on first transfer (in FIFO) */
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if (tx_count == 0)
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dspi_pushr |= SPI_PUSHR_CTCNT;
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
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tx_count++;
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}
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return tx_count * (tx_word + 1);
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}
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static int dspi_eoq_read(struct fsl_dspi *dspi)
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{
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int rx_count = 0;
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int rx_word = is_double_byte_mode(dspi);
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while ((dspi->rx < dspi->rx_end)
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&& (rx_count < DSPI_FIFO_SIZE)) {
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if (rx_word && (dspi->rx_end - dspi->rx) == 1)
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rx_word = 0;
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dspi_data_from_popr(dspi, rx_word);
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rx_count++;
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}
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return rx_count;
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}
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static int dspi_tcfq_write(struct fsl_dspi *dspi)
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{
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int tx_word;
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u32 dspi_pushr = 0;
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tx_word = is_double_byte_mode(dspi);
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if (tx_word && (dspi->len == 1)) {
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
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regmap_update_bits(dspi->regmap, SPI_CTAR(0),
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SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
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tx_word = 0;
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}
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dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
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/* Clear transfer counter on each transfer */
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dspi_pushr |= SPI_PUSHR_CTCNT;
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
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return tx_word + 1;
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regmap_read(dspi->regmap, SPI_POPR, &rxdata);
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return rxdata;
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}
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static void dspi_tcfq_read(struct fsl_dspi *dspi)
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{
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int rx_word = is_double_byte_mode(dspi);
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dspi_push_rx(dspi, fifo_read(dspi));
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}
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if (rx_word && (dspi->rx_end - dspi->rx) == 1)
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rx_word = 0;
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static void dspi_eoq_write(struct fsl_dspi *dspi)
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{
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int fifo_size = DSPI_FIFO_SIZE;
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dspi_data_from_popr(dspi, rx_word);
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/* Fill TX FIFO with as many transfers as possible */
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while (dspi->len && fifo_size--) {
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/* Request EOQF for last transfer in FIFO */
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if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
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dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
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/* Clear transfer count for first transfer in FIFO */
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if (fifo_size == (DSPI_FIFO_SIZE - 1))
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dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
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/* Write combined TX FIFO and CMD FIFO entry */
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fifo_write(dspi);
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}
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}
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static void dspi_eoq_read(struct fsl_dspi *dspi)
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{
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int fifo_size = DSPI_FIFO_SIZE;
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/* Read one FIFO entry at and push to rx buffer */
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while ((dspi->rx < dspi->rx_end) && fifo_size--)
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dspi_push_rx(dspi, fifo_read(dspi));
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}
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static int dspi_transfer_one_message(struct spi_master *master,
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@ -691,19 +633,24 @@ static int dspi_transfer_one_message(struct spi_master *master,
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dspi->void_write_data = dspi->cur_chip->void_write_data;
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dspi->dataflags = 0;
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dspi->tx = (void *)transfer->tx_buf;
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dspi->tx_end = dspi->tx + transfer->len;
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dspi->tx = transfer->tx_buf;
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dspi->rx = transfer->rx_buf;
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dspi->rx_end = dspi->rx + transfer->len;
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dspi->len = transfer->len;
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/* Validated transfer specific frame size (defaults applied) */
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dspi->bits_per_word = transfer->bits_per_word;
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if (transfer->bits_per_word <= 8)
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dspi->bytes_per_word = 1;
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else
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dspi->bytes_per_word = 2;
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regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
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regmap_update_bits(dspi->regmap, SPI_MCR,
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
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regmap_write(dspi->regmap, SPI_CTAR(0),
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dspi->cur_chip->ctar_val);
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dspi->cur_chip->ctar_val |
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SPI_FRAME_BITS(transfer->bits_per_word));
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trans_mode = dspi->devtype_data->trans_mode;
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switch (trans_mode) {
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@ -754,16 +701,9 @@ static int dspi_setup(struct spi_device *spi)
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struct fsl_dspi_platform_data *pdata;
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u32 cs_sck_delay = 0, sck_cs_delay = 0;
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unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
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unsigned char pasc = 0, asc = 0, fmsz = 0;
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unsigned char pasc = 0, asc = 0;
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unsigned long clkrate;
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if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
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fmsz = spi->bits_per_word - 1;
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} else {
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pr_err("Invalid wordsize\n");
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return -ENODEV;
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}
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/* Only alloc on first setup */
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chip = spi_get_ctldata(spi);
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if (chip == NULL) {
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@ -799,8 +739,7 @@ static int dspi_setup(struct spi_device *spi)
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/* Set After SCK delay scale values */
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ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
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chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
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| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
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chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
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| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
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| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
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| SPI_CTAR_PCSSCK(pcssck)
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@ -832,24 +771,19 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
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enum dspi_trans_mode trans_mode;
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u32 spi_sr, spi_tcr;
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u16 spi_tcnt;
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int tx_word;
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regmap_read(dspi->regmap, SPI_SR, &spi_sr);
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regmap_write(dspi->regmap, SPI_SR, spi_sr);
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if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
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tx_word = is_double_byte_mode(dspi);
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/* Get transfer counter (in number of SPI transfers). It was
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* reset to 0 when transfer(s) were started.
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*/
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regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
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spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
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/* Update total number of bytes that were transferred */
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msg->actual_length += spi_tcnt * (tx_word + 1) -
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(dspi->dataflags & TRAN_STATE_WORD_ODD_NUM ? 1 : 0);
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msg->actual_length += spi_tcnt * dspi->bytes_per_word;
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trans_mode = dspi->devtype_data->trans_mode;
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switch (trans_mode) {
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@ -866,14 +800,6 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
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}
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if (!dspi->len) {
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if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
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regmap_update_bits(dspi->regmap,
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SPI_CTAR(0),
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SPI_FRAME_BITS_MASK,
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SPI_FRAME_BITS(16));
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dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
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}
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dspi->waitflags = 1;
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wake_up_interruptible(&dspi->waitq);
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} else {
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@ -973,8 +899,7 @@ static int dspi_probe(struct platform_device *pdev)
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master->cleanup = dspi_cleanup;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
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SPI_BPW_MASK(16);
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
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pdata = dev_get_platdata(&pdev->dev);
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if (pdata) {
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