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crypto: hisilicon - dynamic configuration 'err_info'
'err_info' does not support dynamic configuration since it is const type. Therefore, in order to support new error type later, 'err_info' is changed to dynamic configuration. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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b2a4411aca
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@ -807,6 +807,20 @@ static void hpre_open_axi_master_ooo(struct hisi_qm *qm)
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HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB));
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}
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static void hpre_err_info_init(struct hisi_qm *qm)
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{
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struct hisi_qm_err_info *err_info = &qm->err_info;
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err_info->ce = QM_BASE_CE;
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err_info->fe = 0;
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err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR |
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HPRE_OOO_ECC_2BIT_ERR;
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err_info->dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE;
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err_info->msi_wr_port = HPRE_WR_MSI_PORT;
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err_info->acpi_rst = "HRST";
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err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT;
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}
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static const struct hisi_qm_err_ini hpre_err_ini = {
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.hw_init = hpre_set_user_domain_and_cache,
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.hw_err_enable = hpre_hw_error_enable,
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@ -815,16 +829,7 @@ static const struct hisi_qm_err_ini hpre_err_ini = {
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.clear_dev_hw_err_status = hpre_clear_hw_err_status,
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.log_dev_hw_err = hpre_log_hw_error,
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.open_axi_master_ooo = hpre_open_axi_master_ooo,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT,
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.fe = 0,
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.ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR |
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HPRE_OOO_ECC_2BIT_ERR,
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.dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE,
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.msi_wr_port = HPRE_WR_MSI_PORT,
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.acpi_rst = "HRST",
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}
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.err_info_init = hpre_err_info_init,
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};
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static int hpre_pf_probe_init(struct hpre *hpre)
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@ -837,6 +842,7 @@ static int hpre_pf_probe_init(struct hpre *hpre)
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return ret;
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qm->err_ini = &hpre_err_ini;
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qm->err_ini->err_info_init(qm);
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hisi_qm_dev_err_init(qm);
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return 0;
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@ -1702,7 +1702,7 @@ static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
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if (val == (QM_DB_RANDOM_INVALID | QM_BASE_CE)) {
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writel(error_status, qm->io_base +
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QM_ABNORMAL_INT_SOURCE);
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writel(qm->err_ini->err_info.nfe,
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writel(qm->err_info.nfe,
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qm->io_base + QM_RAS_NFE_ENABLE);
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return ACC_ERR_RECOVERED;
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}
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@ -3107,7 +3107,7 @@ EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
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static void qm_hw_error_init(struct hisi_qm *qm)
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{
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const struct hisi_qm_err_info *err_info = &qm->err_ini->err_info;
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struct hisi_qm_err_info *err_info = &qm->err_info;
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if (!qm->ops->hw_error_init) {
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dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
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@ -3459,15 +3459,15 @@ static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
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/* get device hardware error status */
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err_sts = qm->err_ini->get_dev_hw_err_status(qm);
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if (err_sts) {
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if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)
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if (err_sts & qm->err_info.ecc_2bits_mask)
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qm->err_status.is_dev_ecc_mbit = true;
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if (qm->err_ini->log_dev_hw_err)
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qm->err_ini->log_dev_hw_err(qm, err_sts);
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/* ce error does not need to be reset */
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if ((err_sts | qm->err_ini->err_info.dev_ce_mask) ==
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qm->err_ini->err_info.dev_ce_mask) {
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if ((err_sts | qm->err_info.dev_ce_mask) ==
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qm->err_info.dev_ce_mask) {
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if (qm->err_ini->clear_dev_hw_err_status)
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qm->err_ini->clear_dev_hw_err_status(qm,
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err_sts);
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@ -3780,7 +3780,7 @@ static int qm_soft_reset(struct hisi_qm *qm)
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acpi_status s;
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s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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qm->err_ini->err_info.acpi_rst,
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qm->err_info.acpi_rst,
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NULL, &value);
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if (ACPI_FAILURE(s)) {
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pci_err(pdev, "NO controller reset method!\n");
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@ -3848,12 +3848,11 @@ static void qm_restart_prepare(struct hisi_qm *qm)
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/* temporarily close the OOO port used for PEH to write out MSI */
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value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
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writel(value & ~qm->err_ini->err_info.msi_wr_port,
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writel(value & ~qm->err_info.msi_wr_port,
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qm->io_base + ACC_AM_CFG_PORT_WR_EN);
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/* clear dev ecc 2bit error source if having */
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value = qm_get_dev_err_status(qm) &
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qm->err_ini->err_info.ecc_2bits_mask;
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value = qm_get_dev_err_status(qm) & qm->err_info.ecc_2bits_mask;
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if (value && qm->err_ini->clear_dev_hw_err_status)
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qm->err_ini->clear_dev_hw_err_status(qm, value);
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@ -3877,7 +3876,7 @@ static void qm_restart_done(struct hisi_qm *qm)
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/* open the OOO port for PEH to write out MSI */
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value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
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value |= qm->err_ini->err_info.msi_wr_port;
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value |= qm->err_info.msi_wr_port;
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writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
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qm->err_status.is_qm_ecc_mbit = false;
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@ -4016,8 +4015,7 @@ static int qm_check_dev_error(struct hisi_qm *qm)
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if (ret)
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return ret;
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return (qm_get_dev_err_status(qm) &
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qm->err_ini->err_info.ecc_2bits_mask);
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return (qm_get_dev_err_status(qm) & qm->err_info.ecc_2bits_mask);
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}
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void hisi_qm_reset_prepare(struct pci_dev *pdev)
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@ -186,7 +186,7 @@ struct hisi_qm_err_ini {
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void (*open_axi_master_ooo)(struct hisi_qm *qm);
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void (*close_axi_master_ooo)(struct hisi_qm *qm);
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void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
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struct hisi_qm_err_info err_info;
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void (*err_info_init)(struct hisi_qm *qm);
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};
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struct hisi_qm_list {
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@ -226,6 +226,7 @@ struct hisi_qm {
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struct hisi_qm_status status;
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const struct hisi_qm_err_ini *err_ini;
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struct hisi_qm_err_info err_info;
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struct hisi_qm_err_status err_status;
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unsigned long misc_ctl; /* driver removing and reset sched */
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@ -701,6 +701,20 @@ static void sec_open_axi_master_ooo(struct hisi_qm *qm)
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writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
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}
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static void sec_err_info_init(struct hisi_qm *qm)
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{
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struct hisi_qm_err_info *err_info = &qm->err_info;
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err_info->ce = QM_BASE_CE;
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err_info->fe = 0;
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err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
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err_info->dev_ce_mask = SEC_RAS_CE_ENB_MSK;
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err_info->msi_wr_port = BIT(0);
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err_info->acpi_rst = "SRST";
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err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
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QM_ACC_WB_NOT_READY_TIMEOUT;
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}
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static const struct hisi_qm_err_ini sec_err_ini = {
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.hw_init = sec_set_user_domain_and_cache,
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.hw_err_enable = sec_hw_error_enable,
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@ -709,16 +723,7 @@ static const struct hisi_qm_err_ini sec_err_ini = {
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.clear_dev_hw_err_status = sec_clear_hw_err_status,
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.log_dev_hw_err = sec_log_hw_error,
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.open_axi_master_ooo = sec_open_axi_master_ooo,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
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QM_ACC_WB_NOT_READY_TIMEOUT,
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.fe = 0,
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.ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC,
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.dev_ce_mask = SEC_RAS_CE_ENB_MSK,
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.msi_wr_port = BIT(0),
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.acpi_rst = "SRST",
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}
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.err_info_init = sec_err_info_init,
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};
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static int sec_pf_probe_init(struct sec_dev *sec)
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@ -727,6 +732,7 @@ static int sec_pf_probe_init(struct sec_dev *sec)
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int ret;
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qm->err_ini = &sec_err_ini;
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qm->err_ini->err_info_init(qm);
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ret = sec_set_user_domain_and_cache(qm);
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if (ret)
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@ -657,6 +657,19 @@ static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
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qm->io_base + HZIP_CORE_INT_SET);
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}
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static void hisi_zip_err_info_init(struct hisi_qm *qm)
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{
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struct hisi_qm_err_info *err_info = &qm->err_info;
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err_info->ce = QM_BASE_CE;
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err_info->fe = 0;
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err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC;
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err_info->dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE;
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err_info->msi_wr_port = HZIP_WR_PORT;
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err_info->acpi_rst = "ZRST";
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err_info->nfe = QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT;
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}
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static const struct hisi_qm_err_ini hisi_zip_err_ini = {
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.hw_init = hisi_zip_set_user_domain_and_cache,
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.hw_err_enable = hisi_zip_hw_error_enable,
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@ -666,16 +679,7 @@ static const struct hisi_qm_err_ini hisi_zip_err_ini = {
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.log_dev_hw_err = hisi_zip_log_hw_error,
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.open_axi_master_ooo = hisi_zip_open_axi_master_ooo,
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.close_axi_master_ooo = hisi_zip_close_axi_master_ooo,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE |
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QM_ACC_WB_NOT_READY_TIMEOUT,
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.fe = 0,
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.ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC,
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.dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE,
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.msi_wr_port = HZIP_WR_PORT,
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.acpi_rst = "ZRST",
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}
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.err_info_init = hisi_zip_err_info_init,
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};
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static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
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@ -690,6 +694,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
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hisi_zip->ctrl = ctrl;
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ctrl->hisi_zip = hisi_zip;
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qm->err_ini = &hisi_zip_err_ini;
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qm->err_ini->err_info_init(qm);
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hisi_zip_set_user_domain_and_cache(qm);
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hisi_qm_dev_err_init(qm);
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