Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-23 12:42:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

Microchip RISC-V devicetree fixes for 6.0-rc4 (or later)

Browse Source 
A fix for the warnings introduced in rc3 as part of fixing the console
 spam from the L2's isr.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCYxInHAAKCRB4tDGHoIJi
 0o9XAP9BHgmKQy9AwCkUb+Dg5VGBYNFgxDw7a2eVoMf/GolLOwEAoDXSyCMgBXhP
 oyaI5e30JmaxZIs7fPB+T1EERxZ5Cg4=
 =8oTN
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAmMTq28THHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQW1jEACV0vJNhaJXq7+sccHld/h0fCb1NuiH
 STvGkI3aHSY8B8IriuGnoalo9l2dtwB1/Yu/m/R28CooOyr8KYSPtsuUGwOegW4E
 XCmLjztj8dgwYJq/gI/xrzQR7HJ6TLeJDuC/xXi/7GQU+zqsPFI/MGeO5UW1tzsh
 t3iuXK7oMPGefQx+qWe/5h2/GLNYDEKzt1b6BvdgjMwh4mA0BcSxOzc8ABdlCXOS
 368e0ONfDyFcxzeUso4h5diiiN0Jrp9AwQd6OeYo4c+mHmpq2+3WeHvfPJxYwVJW
 56j9k3elK46YveeIsyG4/EJx65TtQQhZfrJzr1kZI7vfpEwcXbqrhXN/+SBIf1Sc
 MsV98GWcuxrxNxGFsl52CVGSWdhiqohna3lyIcX9CQFYud0K00HdxlTQpUqx8e20
 PP2/jYvBwWnEmOGs7VhGPYNtcn9mF9lZ+r8DJ02c3eunQnGDtesBGKd4i+xUTaUY
 gxq8+q6KO0pI8z206JjuGwvmxbkox8D30xjP/PIzWM8IKd6hQ2DjVRXauGWtynwT
 ws3tcC4YMQlJN8YPK/hjck9gk7RVqm6XvGLpkMw9Eu2ewqdBJC7gvtgMxZDeReMr
 LOoSFpcOYV++lUnBjNDDWrVXGNHGL+AohereTIIEGukME6eRPYH4xYvubHgLSCSH
 q+D3IpBkjMCg2Q==
 =dwLh
 -----END PGP SIGNATURE-----

Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes

Microchip RISC-V devicetree fixes for 6.0-rc4 (or later)

A fix for the warnings introduced in rc3 as part of fixing the console
spam from the L2's isr.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
  riscv: dts: microchip: use an mpfs specific l2 compatible
  dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
This commit is contained in:
Palmer Dabbelt 2022-09-03 12:30:23 -07:00
commit d958edb9ee
2 changed files with 49 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
View File

@ -17,9 +17,6 @@ description:
acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform.
allOf:
- $ref: /schemas/cache-controller.yaml#
select:
properties:
compatible:
@ -33,11 +30,16 @@ select:
properties:
compatible:
items:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
oneOf:
- items:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
cache-block-size:
const: 64
@ -72,29 +74,46 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
if:
properties:
compatible:
contains:
const: sifive,fu540-c000-ccache
allOf:
- $ref: /schemas/cache-controller.yaml#
then:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
cache-sets:
const: 1024
- if:
properties:
compatible:
contains:
enum:
- sifive,fu740-c000-ccache
- microchip,mpfs-ccache
else:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
cache-sets:
const: 2048
then:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
else:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
- if:
properties:
compatible:
contains:
const: sifive,fu740-c000-ccache
then:
properties:
cache-sets:
const: 2048
else:
properties:
cache-sets:
const: 1024
additionalProperties: false

2
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -185,7 +185,7 @@
ranges;
cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;