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MIPS: Loongson64: DTS: Fix PCIe port nodes for ls7a

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Add various required properties to silent warnings:

arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi:116.16-297.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider
arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider'

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang 2024-05-07 19:51:22 +01:00 committed by Thomas Bogendoerfer
parent 98a9e2ac37
commit d89a415ff8
1 changed files with 30 additions and 7 deletions
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37
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
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@ -118,7 +118,6 @@
device_type = "pci"; device_type = "pci";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <2>;
reg = <0 0x1a000000 0 0x02000000>, reg = <0 0x1a000000 0 0x02000000>,
<0xfe 0x00000000 0 0x20000000>; <0xfe 0x00000000 0 0x20000000>;
@ -204,93 +203,117 @@
interrupt-parent = <&liointc0>; interrupt-parent = <&liointc0>;
}; };
pci_bridge@9,0 { pcie@9,0 {
compatible = "pci0014,7a19.0", compatible = "pci0014,7a19.0",
"pci0014,7a19", "pci0014,7a19",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x4800 0x0 0x0 0x0 0x0>; reg = <0x4800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };
pci_bridge@a,0 { pcie@a,0 {
compatible = "pci0014,7a09.0", compatible = "pci0014,7a09.0",
"pci0014,7a09", "pci0014,7a09",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x5000 0x0 0x0 0x0 0x0>; reg = <0x5000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };
pci_bridge@b,0 { pcie@b,0 {
compatible = "pci0014,7a09.0", compatible = "pci0014,7a09.0",
"pci0014,7a09", "pci0014,7a09",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x5800 0x0 0x0 0x0 0x0>; reg = <0x5800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };
pci_bridge@c,0 { pcie@c,0 {
compatible = "pci0014,7a09.0", compatible = "pci0014,7a09.0",
"pci0014,7a09", "pci0014,7a09",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x6000 0x0 0x0 0x0 0x0>; reg = <0x6000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };
pci_bridge@d,0 { pcie@d,0 {
compatible = "pci0014,7a19.0", compatible = "pci0014,7a19.0",
"pci0014,7a19", "pci0014,7a19",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x6800 0x0 0x0 0x0 0x0>; reg = <0x6800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };
pci_bridge@e,0 { pcie@e,0 {
compatible = "pci0014,7a09.0", compatible = "pci0014,7a09.0",
"pci0014,7a09", "pci0014,7a09",
"pciclass060400", "pciclass060400",
"pciclass0604"; "pciclass0604";
reg = <0x7000 0x0 0x0 0x0 0x0>; reg = <0x7000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&liointc1>; interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
ranges;
external-facing; external-facing;
}; };