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KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler
Add a handler for reading/writing the guest's view of the ICV_CTLR_EL1 register. only EOIMode and CBPR are of interest here, as all the other bits directly come from ICH_VTR_EL2 and are Read-Only. Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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@ -891,6 +891,46 @@ static void __hyp_text __vgic_v3_read_rpr(struct kvm_vcpu *vcpu,
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vcpu_set_reg(vcpu, rt, val);
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}
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static void __hyp_text __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
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u32 vmcr, int rt)
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{
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u32 vtr, val;
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vtr = read_gicreg(ICH_VTR_EL2);
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/* PRIbits */
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val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
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/* IDbits */
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val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
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/* SEIS */
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val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
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/* A3V */
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val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
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/* EOImode */
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val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
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/* CBPR */
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val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
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vcpu_set_reg(vcpu, rt, val);
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}
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static void __hyp_text __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu,
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u32 vmcr, int rt)
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{
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u32 val = vcpu_get_reg(vcpu, rt);
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if (val & ICC_CTLR_EL1_CBPR_MASK)
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vmcr |= ICH_VMCR_CBPR_MASK;
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else
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vmcr &= ~ICH_VMCR_CBPR_MASK;
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if (val & ICC_CTLR_EL1_EOImode_MASK)
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vmcr |= ICH_VMCR_EOIM_MASK;
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else
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vmcr &= ~ICH_VMCR_EOIM_MASK;
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write_gicreg(vmcr, ICH_VMCR_EL2);
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}
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int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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{
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int rt;
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@ -983,6 +1023,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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case SYS_ICC_RPR_EL1:
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fn = __vgic_v3_read_rpr;
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break;
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case SYS_ICC_CTLR_EL1:
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if (is_read)
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fn = __vgic_v3_read_ctlr;
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else
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fn = __vgic_v3_write_ctlr;
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break;
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default:
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return 0;
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}
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