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mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
Add support for the NAND flash controller found on NVIDIA Tegra 2 SoCs. This implementation does not make use of the command queue feature. Regular operations using ->exec_op() use PIO mode for data transfers. Raw, ECC and OOB read/writes make use of the DMA mode for data transfer. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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@ -14054,6 +14054,13 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
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S: Supported
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F: drivers/input/keyboard/tegra-kbc.c
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TEGRA NAND DRIVER
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M: Stefan Agner <stefan@agner.ch>
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M: Lucas Stach <dev@lynxeye.de>
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S: Maintained
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F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
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F: drivers/mtd/nand/raw/tegra_nand.c
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TEGRA PWM DRIVER
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M: Thierry Reding <thierry.reding@gmail.com>
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S: Supported
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@ -530,4 +530,14 @@ config MTD_NAND_MTK
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Enables support for NAND controller on MTK SoCs.
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This controller is found on mt27xx, mt81xx, mt65xx SoCs.
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config MTD_NAND_TEGRA
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tristate "Support for NAND controller on NVIDIA Tegra"
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depends on ARCH_TEGRA || COMPILE_TEST
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help
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Enables support for NAND flash controller on NVIDIA Tegra SoC.
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The driver has been developed and tested on a Tegra 2 SoC. DMA
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support, raw read/write page as well as HW ECC read/write page
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is supported. Extra OOB bytes when using HW ECC are currently
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not supported.
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endif # MTD_NAND
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@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
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obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
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obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
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obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
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obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
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nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
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nand-objs += nand_amd.o
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1230
drivers/mtd/nand/raw/tegra_nand.c
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1230
drivers/mtd/nand/raw/tegra_nand.c
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