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Merge branch 'use-mmd-c45-helpers'

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Andrew Lunn says:

====================
Use MMD/C45 helpers

MDIO busses can perform two sorts of bus transaction, defined in
clause 22 and clause 45 of 802.3. This results in two register
addresses spaces. The current driver structure for indicating if C22
or C45 should be used is messy, and many C22 only bus drivers will
wrongly interpret a C45 transaction as a C22 transaction.

This patchset is a preparation step to cleanup the situation. It
converts MDIO bus users to make use of existing _mmd and _c45 helpers
to perform accesses to C45 registers. This will later allow C45 and
C22 to be kept separate.
====================

Link: https://lore.kernel.org/r/20220430173037.156823-1-andrew@lunn.ch
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2022-05-02 13:21:40 +02:00
commit d7ab15ab34
5 changed files with 52 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/net/dsa/sja1105/sja1105_main.c
View File

@ -2252,14 +2252,13 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
* change it through the dynamic interface later.
*/
for (i = 0; i < ds->num_ports; i++) {
u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
mac[i].speed);
mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
if (priv->xpcs[i])
bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
MDIO_MMD_VEND2, MDIO_CTRL1);
}
/* No PTP operations can run right now */

6
drivers/net/pcs/pcs-xpcs.c
View File

@ -175,20 +175,18 @@ static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
{
u32 reg_addr = mdiobus_c45_addr(dev, reg);
struct mii_bus *bus = xpcs->mdiodev->bus;
int addr = xpcs->mdiodev->addr;
return mdiobus_read(bus, addr, reg_addr);
return mdiobus_c45_read(bus, addr, dev, reg);
}
int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
{
u32 reg_addr = mdiobus_c45_addr(dev, reg);
struct mii_bus *bus = xpcs->mdiodev->bus;
int addr = xpcs->mdiodev->addr;
return mdiobus_write(bus, addr, reg_addr, val);
return mdiobus_c45_write(bus, addr, dev, reg, val);
}
static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)

36
drivers/net/phy/bcm87xx.c
View File

@ -10,12 +10,12 @@
#define PHY_ID_BCM8706 0x0143bdc1
#define PHY_ID_BCM8727 0x0143bff0
#define BCM87XX_PMD_RX_SIGNAL_DETECT (MII_ADDR_C45 | 0x1000a)
#define BCM87XX_10GBASER_PCS_STATUS (MII_ADDR_C45 | 0x30020)
#define BCM87XX_XGXS_LANE_STATUS (MII_ADDR_C45 | 0x40018)
#define BCM87XX_PMD_RX_SIGNAL_DETECT 0x000a
#define BCM87XX_10GBASER_PCS_STATUS 0x0020
#define BCM87XX_XGXS_LANE_STATUS 0x0018
#define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002)
#define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005)
#define BCM87XX_LASI_CONTROL 0x9002
#define BCM87XX_LASI_STATUS 0x9005
#if IS_ENABLED(CONFIG_OF_MDIO)
/* Set and/or override some configuration registers based on the
@ -54,11 +54,10 @@ static int bcm87xx_of_reg_init(struct phy_device *phydev)
u16 reg = be32_to_cpup(paddr++);
u16 mask = be32_to_cpup(paddr++);
u16 val_bits = be32_to_cpup(paddr++);
u32 regnum = mdiobus_c45_addr(devid, reg);
int val = 0;
if (mask) {
val = phy_read(phydev, regnum);
val = phy_read_mmd(phydev, devid, reg);
if (val < 0) {
ret = val;
goto err;
@ -67,7 +66,7 @@ static int bcm87xx_of_reg_init(struct phy_device *phydev)
}
val |= val_bits;
ret = phy_write(phydev, regnum, val);
ret = phy_write_mmd(phydev, devid, reg, val);
if (ret < 0)
goto err;
}
@ -104,21 +103,24 @@ static int bcm87xx_read_status(struct phy_device *phydev)
int pcs_status;
int xgxs_lane_status;
rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT);
rx_signal_detect = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
BCM87XX_PMD_RX_SIGNAL_DETECT);
if (rx_signal_detect < 0)
return rx_signal_detect;
if ((rx_signal_detect & 1) == 0)
goto no_link;
pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS);
pcs_status = phy_read_mmd(phydev, MDIO_MMD_PCS,
BCM87XX_10GBASER_PCS_STATUS);
if (pcs_status < 0)
return pcs_status;
if ((pcs_status & 1) == 0)
goto no_link;
xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS);
xgxs_lane_status = phy_read_mmd(phydev, MDIO_MMD_PHYXS,
BCM87XX_XGXS_LANE_STATUS);
if (xgxs_lane_status < 0)
return xgxs_lane_status;
@ -139,25 +141,27 @@ static int bcm87xx_config_intr(struct phy_device *phydev)
{
int reg, err;
reg = phy_read(phydev, BCM87XX_LASI_CONTROL);
reg = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_CONTROL);
if (reg < 0)
return reg;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
err = phy_read(phydev, BCM87XX_LASI_STATUS);
err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
if (err)
return err;
reg |= 1;
err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg);
err = phy_write_mmd(phydev, MDIO_MMD_PCS,
BCM87XX_LASI_CONTROL, reg);
} else {
reg &= ~1;
err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg);
err = phy_write_mmd(phydev, MDIO_MMD_PCS,
BCM87XX_LASI_CONTROL, reg);
if (err)
return err;
err = phy_read(phydev, BCM87XX_LASI_STATUS);
err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
}
return err;

18
drivers/net/phy/phy.c
View File

@ -295,20 +295,20 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
if (mdio_phy_id_is_c45(mii_data->phy_id)) {
prtad = mdio_phy_id_prtad(mii_data->phy_id);
devad = mdio_phy_id_devad(mii_data->phy_id);
devad = mdiobus_c45_addr(devad, mii_data->reg_num);
mii_data->val_out = mdiobus_c45_read(
phydev->mdio.bus, prtad, devad,
mii_data->reg_num);
} else {
prtad = mii_data->phy_id;
devad = mii_data->reg_num;
mii_data->val_out = mdiobus_read(
phydev->mdio.bus, mii_data->phy_id,
mii_data->reg_num);
}
mii_data->val_out = mdiobus_read(phydev->mdio.bus, prtad,
devad);
return 0;
case SIOCSMIIREG:
if (mdio_phy_id_is_c45(mii_data->phy_id)) {
prtad = mdio_phy_id_prtad(mii_data->phy_id);
devad = mdio_phy_id_devad(mii_data->phy_id);
devad = mdiobus_c45_addr(devad, mii_data->reg_num);
} else {
prtad = mii_data->phy_id;
devad = mii_data->reg_num;
@ -351,7 +351,11 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
}
}
mdiobus_write(phydev->mdio.bus, prtad, devad, val);
if (mdio_phy_id_is_c45(mii_data->phy_id))
mdiobus_c45_write(phydev->mdio.bus, prtad, devad,
mii_data->reg_num, val);
else
mdiobus_write(phydev->mdio.bus, prtad, devad, val);
if (prtad == phydev->mdio.addr &&
devad == MII_BMCR &&

32
drivers/net/phy/phylink.c
View File

@ -2303,8 +2303,11 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id,
if (mdio_phy_id_is_c45(phy_id)) {
prtad = mdio_phy_id_prtad(phy_id);
devad = mdio_phy_id_devad(phy_id);
devad = mdiobus_c45_addr(devad, reg);
} else if (phydev->is_c45) {
return mdiobus_c45_read(pl->phydev->mdio.bus, prtad, devad,
reg);
}
if (phydev->is_c45) {
switch (reg) {
case MII_BMCR:
case MII_BMSR:
@ -2326,12 +2329,11 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id,
return -EINVAL;
}
prtad = phy_id;
devad = mdiobus_c45_addr(devad, reg);
} else {
prtad = phy_id;
devad = reg;
return mdiobus_c45_read(pl->phydev->mdio.bus, prtad, devad,
reg);
}
return mdiobus_read(pl->phydev->mdio.bus, prtad, devad);
return mdiobus_read(pl->phydev->mdio.bus, phy_id, reg);
}
static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
@ -2343,8 +2345,11 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
if (mdio_phy_id_is_c45(phy_id)) {
prtad = mdio_phy_id_prtad(phy_id);
devad = mdio_phy_id_devad(phy_id);
devad = mdiobus_c45_addr(devad, reg);
} else if (phydev->is_c45) {
return mdiobus_c45_write(pl->phydev->mdio.bus, prtad, devad,
reg, val);
}
if (phydev->is_c45) {
switch (reg) {
case MII_BMCR:
case MII_BMSR:
@ -2365,14 +2370,11 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
default:
return -EINVAL;
}
prtad = phy_id;
devad = mdiobus_c45_addr(devad, reg);
} else {
prtad = phy_id;
devad = reg;
return mdiobus_c45_write(pl->phydev->mdio.bus, phy_id, devad,
reg, val);
}
return mdiobus_write(phydev->mdio.bus, prtad, devad, val);
return mdiobus_write(phydev->mdio.bus, phy_id, reg, val);
}
static int phylink_mii_read(struct phylink *pl, unsigned int phy_id,