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KVM: Allow aligned byte and word writes to IOAPIC registers.

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This fixes byte accesses to IOAPIC_REG_SELECT as mandated by at least the
ICH10 and Intel Series 5 chipset specs. It also makes ioapic_mmio_write
consistent with ioapic_mmio_read, which also allows byte and word accesses.

Signed-off-by: Julian Stecklina <js@alien8.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Julian Stecklina 2011-11-23 13:54:30 +01:00 committed by Avi Kivity
parent 60f9a9ef54
commit d77fe6354d
1 changed files with 12 additions and 3 deletions
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15
virt/kvm/ioapic.c
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@ -332,9 +332,18 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
(void*)addr, len, val); (void*)addr, len, val);
ASSERT(!(addr & 0xf)); /* check alignment */ ASSERT(!(addr & 0xf)); /* check alignment */
if (len == 4 || len == 8) switch (len) {
case 8:
case 4:
data = *(u32 *) val; data = *(u32 *) val;
else { break;
case 2:
data = *(u16 *) val;
break;
case 1:
data = *(u8 *) val;
break;
default:
printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
return 0; return 0;
} }
@ -343,7 +352,7 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
spin_lock(&ioapic->lock); spin_lock(&ioapic->lock);
switch (addr) { switch (addr) {
case IOAPIC_REG_SELECT: case IOAPIC_REG_SELECT:
ioapic->ioregsel = data; ioapic->ioregsel = data & 0xFF; /* 8-bit register */
break; break;
case IOAPIC_REG_WINDOW: case IOAPIC_REG_WINDOW: