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dt-bindings: clock: r9a07g044-cpg: Add power domain IDs

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Add power domain IDs for the RZ/G2L (R9A07G044) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2024-04-22 13:53:49 +03:00 committed by Geert Uytterhoeven
parent b6cc692ac6
commit d744e45674
1 changed files with 58 additions and 0 deletions
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58
include/dt-bindings/clock/r9a07g044-cpg.h
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@ -217,4 +217,62 @@
#define R9A07G044_ADC_ADRST_N 82 #define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83 #define R9A07G044_TSU_PRESETN 83
/* Power domain IDs. */
#define R9A07G044_PD_ALWAYS_ON 0
#define R9A07G044_PD_GIC 1
#define R9A07G044_PD_IA55 2
#define R9A07G044_PD_MHU 3
#define R9A07G044_PD_CORESIGHT 4
#define R9A07G044_PD_SYC 5
#define R9A07G044_PD_DMAC 6
#define R9A07G044_PD_GTM0 7
#define R9A07G044_PD_GTM1 8
#define R9A07G044_PD_GTM2 9
#define R9A07G044_PD_MTU 10
#define R9A07G044_PD_POE3 11
#define R9A07G044_PD_GPT 12
#define R9A07G044_PD_POEGA 13
#define R9A07G044_PD_POEGB 14
#define R9A07G044_PD_POEGC 15
#define R9A07G044_PD_POEGD 16
#define R9A07G044_PD_WDT0 17
#define R9A07G044_PD_WDT1 18
#define R9A07G044_PD_SPI 19
#define R9A07G044_PD_SDHI0 20
#define R9A07G044_PD_SDHI1 21
#define R9A07G044_PD_3DGE 22
#define R9A07G044_PD_ISU 23
#define R9A07G044_PD_VCPL4 24
#define R9A07G044_PD_CRU 25
#define R9A07G044_PD_MIPI_DSI 26
#define R9A07G044_PD_LCDC 27
#define R9A07G044_PD_SSI0 28
#define R9A07G044_PD_SSI1 29
#define R9A07G044_PD_SSI2 30
#define R9A07G044_PD_SSI3 31
#define R9A07G044_PD_SRC 32
#define R9A07G044_PD_USB0 33
#define R9A07G044_PD_USB1 34
#define R9A07G044_PD_USB_PHY 35
#define R9A07G044_PD_ETHER0 36
#define R9A07G044_PD_ETHER1 37
#define R9A07G044_PD_I2C0 38
#define R9A07G044_PD_I2C1 39
#define R9A07G044_PD_I2C2 40
#define R9A07G044_PD_I2C3 41
#define R9A07G044_PD_SCIF0 42
#define R9A07G044_PD_SCIF1 43
#define R9A07G044_PD_SCIF2 44
#define R9A07G044_PD_SCIF3 45
#define R9A07G044_PD_SCIF4 46
#define R9A07G044_PD_SCI0 47
#define R9A07G044_PD_SCI1 48
#define R9A07G044_PD_IRDA 49
#define R9A07G044_PD_RSPI0 50
#define R9A07G044_PD_RSPI1 51
#define R9A07G044_PD_RSPI2 52
#define R9A07G044_PD_CANFD 53
#define R9A07G044_PD_ADC 54
#define R9A07G044_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */