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ocxl: Update the Process Element Entry

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To complete the MMIO based mechanism, the fields: PASID, bus, device and
function of the Process Element Entry have to be filled. (See
OpenCAPI Power Platform Architecture document)

                   Hypervisor Process Element Entry
Word
    0 1 .... 7  8  ...... 12  13 ..15  16.... 19  20 ........... 31
0                  OSL Configuration State (0:31)
1                  OSL Configuration State (32:63)
2               PASID                      |    Reserved
3       Bus   |   Device    |Function |        Reserved
4                             Reserved
5                             Reserved
6                               ....

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201125155013.39955-4-clombard@linux.vnet.ibm.com
This commit is contained in:
Christophe Lombard 2020-11-25 16:50:11 +01:00 committed by Michael Ellerman
parent 19b311ca51
commit d731feea00
5 changed files with 17 additions and 8 deletions
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4
drivers/misc/ocxl/context.c
View File

@ -70,6 +70,7 @@ int ocxl_context_attach(struct ocxl_context *ctx, u64 amr, struct mm_struct *mm)
{
int rc;
unsigned long pidr = 0;
struct pci_dev *dev;
// Locks both status & tidr
mutex_lock(&ctx->status_mutex);
@ -81,8 +82,9 @@ int ocxl_context_attach(struct ocxl_context *ctx, u64 amr, struct mm_struct *mm)
if (mm)
pidr = mm->context.id;
dev = to_pci_dev(ctx->afu->fn->dev.parent);
rc = ocxl_link_add_pe(ctx->afu->fn->link, ctx->pasid, pidr, ctx->tidr,
amr, mm, xsl_fault_error, ctx);
amr, pci_dev_id(dev), mm, xsl_fault_error, ctx);
if (rc)
goto out;

4
drivers/misc/ocxl/link.c
View File

@ -494,7 +494,7 @@ static u64 calculate_cfg_state(bool kernel)
}
int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
u64 amr, struct mm_struct *mm,
u64 amr, u16 bdf, struct mm_struct *mm,
void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
void *xsl_err_data)
{
@ -529,6 +529,8 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
memset(pe, 0, sizeof(struct ocxl_process_element));
pe->config_state = cpu_to_be64(calculate_cfg_state(pidr == 0));
pe->pasid = cpu_to_be32(pasid << (31 - 19));
pe->bdf = cpu_to_be16(bdf);
pe->lpid = cpu_to_be32(mfspr(SPRN_LPID));
pe->pid = cpu_to_be32(pidr);
pe->tid = cpu_to_be32(tidr);

9
drivers/misc/ocxl/ocxl_internal.h
View File

@ -84,13 +84,16 @@ struct ocxl_context {
struct ocxl_process_element {
__be64 config_state;
__be32 reserved1[11];
__be32 pasid;
__be16 bdf;
__be16 reserved1;
__be32 reserved2[9];
__be32 lpid;
__be32 tid;
__be32 pid;
__be32 reserved2[10];
__be32 reserved3[10];
__be64 amr;
__be32 reserved3[3];
__be32 reserved4[3];
__be32 software_state;
};

6
drivers/scsi/cxlflash/ocxl_hw.c
View File

@ -329,6 +329,7 @@ static int start_context(struct ocxlflash_context *ctx)
struct ocxl_hw_afu *afu = ctx->hw_afu;
struct ocxl_afu_config *acfg = &afu->acfg;
void *link_token = afu->link_token;
struct pci_dev *pdev = afu->pdev;
struct device *dev = afu->dev;
bool master = ctx->master;
struct mm_struct *mm;
@ -360,8 +361,9 @@ static int start_context(struct ocxlflash_context *ctx)
mm = current->mm;
}
rc = ocxl_link_add_pe(link_token, ctx->pe, pid, 0, 0, mm,
ocxlflash_xsl_fault, ctx);
rc = ocxl_link_add_pe(link_token, ctx->pe, pid, 0, 0,
pci_dev_id(pdev), mm, ocxlflash_xsl_fault,
ctx);
if (unlikely(rc)) {
dev_err(dev, "%s: ocxl_link_add_pe failed rc=%d\n",
__func__, rc);

2
include/misc/ocxl.h
View File

@ -447,7 +447,7 @@ void ocxl_link_release(struct pci_dev *dev, void *link_handle);
* defined
*/
int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
u64 amr, struct mm_struct *mm,
u64 amr, u16 bdf, struct mm_struct *mm,
void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
void *xsl_err_data);