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drm/sun4i: tcon: Support LVDS output on Allwinner A20
A20 SoC (found in Cubieboard 2 among others) requires different LVDS set up procedure than A33. Timing controller (tcon) driver only implements sun6i-style procedure, that doesn't work on A20 (sun7i). Signed-off-by: Andrey Lebedev <andrey@lebedev.lt> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20200219180858.4806-6-andrey.lebedev@gmail.com
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@ -114,6 +114,30 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
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}
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}
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static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
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const struct drm_encoder *encoder)
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{
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regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
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SUN4I_TCON0_LVDS_ANA0_CK_EN |
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SUN4I_TCON0_LVDS_ANA0_REG_V |
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SUN4I_TCON0_LVDS_ANA0_REG_C |
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SUN4I_TCON0_LVDS_ANA0_EN_MB |
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SUN4I_TCON0_LVDS_ANA0_PD |
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SUN4I_TCON0_LVDS_ANA0_DCHS);
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udelay(2); /* delay at least 1200 ns */
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regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
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SUN4I_TCON0_LVDS_ANA1_INIT,
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SUN4I_TCON0_LVDS_ANA1_INIT);
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udelay(1); /* delay at least 120 ns */
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regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
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SUN4I_TCON0_LVDS_ANA1_UPDATE,
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SUN4I_TCON0_LVDS_ANA1_UPDATE);
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regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
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SUN4I_TCON0_LVDS_ANA0_EN_MB,
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SUN4I_TCON0_LVDS_ANA0_EN_MB);
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}
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static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
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const struct drm_encoder *encoder)
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{
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@ -1454,6 +1478,16 @@ static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
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.dclk_min_div = 1,
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};
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static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = {
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.supports_lvds = true,
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.has_channel_0 = true,
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.has_channel_1 = true,
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.dclk_min_div = 4,
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/* Same display pipeline structure as A10 */
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.set_mux = sun4i_a10_tcon_set_mux,
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.setup_lvds_phy = sun4i_tcon_setup_lvds_phy,
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};
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static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
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.has_channel_0 = true,
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.has_channel_1 = true,
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@ -1508,7 +1542,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
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{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
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{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
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{ .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
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{ .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_quirks },
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{ .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
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{ .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
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{ .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
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{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
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@ -193,6 +193,13 @@
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#define SUN4I_TCON_MUX_CTRL_REG 0x200
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#define SUN4I_TCON0_LVDS_ANA0_REG 0x220
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#define SUN4I_TCON0_LVDS_ANA0_DCHS BIT(16)
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#define SUN4I_TCON0_LVDS_ANA0_PD (BIT(20) | BIT(21))
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#define SUN4I_TCON0_LVDS_ANA0_EN_MB BIT(22)
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#define SUN4I_TCON0_LVDS_ANA0_REG_C (BIT(24) | BIT(25))
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#define SUN4I_TCON0_LVDS_ANA0_REG_V (BIT(26) | BIT(27))
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#define SUN4I_TCON0_LVDS_ANA0_CK_EN (BIT(29) | BIT(28))
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#define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31)
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#define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
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#define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
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@ -201,6 +208,10 @@
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#define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
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#define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4)
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#define SUN4I_TCON0_LVDS_ANA1_REG 0x224
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#define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f << 10)
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#define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f << 00)
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#define SUN4I_TCON1_FILL_CTL_REG 0x300
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#define SUN4I_TCON1_FILL_BEG0_REG 0x304
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#define SUN4I_TCON1_FILL_END0_REG 0x308
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