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drm/radeon/kms: add dpm support for trinity asics

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This adds dpm support for trinity asics.  This includes:
- clockgating
- powergating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-04-12 16:40:41 -04:00
parent 80ea2c129c
commit d70229f704
14 changed files with 2179 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/radeon/Makefile
View File

@ -78,7 +78,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
trinity_smc.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

13
drivers/gpu/drm/radeon/evergreen.c
View File

@ -4187,8 +4187,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
thermal_int = RREG32(CG_THERMAL_INT) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
if (rdev->family == CHIP_ARUBA)
thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
else
thermal_int = RREG32(CG_THERMAL_INT) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
@ -4360,7 +4364,10 @@ int evergreen_irq_set(struct radeon_device *rdev)
WREG32(DC_HPD4_INT_CONTROL, hpd4);
WREG32(DC_HPD5_INT_CONTROL, hpd5);
WREG32(DC_HPD6_INT_CONTROL, hpd6);
WREG32(CG_THERMAL_INT, thermal_int);
if (rdev->family == CHIP_ARUBA)
WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);
else
WREG32(CG_THERMAL_INT, thermal_int);
WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);

10
drivers/gpu/drm/radeon/evergreend.h
View File

@ -823,6 +823,16 @@
#define THERM_INT_MASK_HIGH (1 << 24)
#define THERM_INT_MASK_LOW (1 << 25)
#define TN_CG_THERMAL_INT_CTRL 0x738
#define TN_DIG_THERM_INTH(x) ((x) << 0)
#define TN_DIG_THERM_INTH_MASK 0x000000FF
#define TN_DIG_THERM_INTH_SHIFT 0
#define TN_DIG_THERM_INTL(x) ((x) << 8)
#define TN_DIG_THERM_INTL_MASK 0x0000FF00
#define TN_DIG_THERM_INTL_SHIFT 8
#define TN_THERM_INT_MASK_HIGH (1 << 24)
#define TN_THERM_INT_MASK_LOW (1 << 25)
#define CG_MULT_THERMAL_STATUS 0x740
#define ASIC_T(x) ((x) << 16)
#define ASIC_T_MASK 0x07FF0000

10
drivers/gpu/drm/radeon/ppsmc.h
View File

@ -71,7 +71,15 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_MSG_ExitULV ((uint8_t)0x65)
#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)
typedef uint8_t PPSMC_Msg;
/* TN */
#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)
#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104)
#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
typedef uint16_t PPSMC_Msg;
#pragma pack(pop)

12
drivers/gpu/drm/radeon/radeon_asic.c
View File

@ -2064,6 +2064,18 @@ static struct radeon_asic trinity_asic = {
.set_uvd_clocks = &sumo_set_uvd_clocks,
.get_temperature = &tn_get_temp,
},
.dpm = {
.init = &trinity_dpm_init,
.setup_asic = &trinity_dpm_setup_asic,
.enable = &trinity_dpm_enable,
.disable = &trinity_dpm_disable,
.set_power_state = &trinity_dpm_set_power_state,
.display_configuration_changed = &trinity_dpm_display_configuration_changed,
.fini = &trinity_dpm_fini,
.get_sclk = &trinity_dpm_get_sclk,
.get_mclk = &trinity_dpm_get_mclk,
.print_power_state = &trinity_dpm_print_power_state,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
.page_flip = &evergreen_page_flip,

12
drivers/gpu/drm/radeon/radeon_asic.h
View File

@ -587,6 +587,18 @@ bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
int trinity_dpm_init(struct radeon_device *rdev);
int trinity_dpm_enable(struct radeon_device *rdev);
void trinity_dpm_disable(struct radeon_device *rdev);
int trinity_dpm_set_power_state(struct radeon_device *rdev);
void trinity_dpm_setup_asic(struct radeon_device *rdev);
void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
void trinity_dpm_fini(struct radeon_device *rdev);
u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
void trinity_dpm_print_power_state(struct radeon_device *rdev,
struct radeon_ps *ps);
/* DCE6 - SI */
void dce6_bandwidth_update(struct radeon_device *rdev);

1
drivers/gpu/drm/radeon/radeon_pm.c
View File

@ -1052,6 +1052,7 @@ int radeon_pm_init(struct radeon_device *rdev)
case CHIP_BARTS:
case CHIP_TURKS:
case CHIP_CAICOS:
case CHIP_ARUBA:
if (radeon_dpm == 1)
rdev->pm.pm_method = PM_METHOD_DPM;
else

90
drivers/gpu/drm/radeon/sumo_dpm.c
View File

@ -27,7 +27,6 @@
#include "r600_dpm.h"
#include "cypress_dpm.h"
#include "sumo_dpm.h"
#include "atom.h"
#define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
#define SUMO_MINIMUM_ENGINE_CLOCK 800
@ -144,7 +143,7 @@ static void sumo_program_grsd(struct radeon_device *rdev)
WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
}
static void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
{
sumo_program_git(rdev);
sumo_program_grsd(rdev);
@ -452,17 +451,17 @@ static void sumo_program_tp(struct radeon_device *rdev)
WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
}
static void sumo_program_vc(struct radeon_device *rdev)
void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
{
WREG32(CG_FTV, SUMO_VRC_DFLT);
WREG32(CG_FTV, vrc);
}
static void sumo_clear_vc(struct radeon_device *rdev)
void sumo_clear_vc(struct radeon_device *rdev)
{
WREG32(CG_FTV, 0);
}
static void sumo_program_sstp(struct radeon_device *rdev)
void sumo_program_sstp(struct radeon_device *rdev)
{
u32 p, u;
u32 xclk = sumo_get_xclk(rdev);
@ -812,7 +811,7 @@ static void sumo_program_bootup_state(struct radeon_device *rdev)
sumo_power_level_enable(rdev, i, false);
}
static void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
{
u32 v = RREG32(DOUT_SCRATCH3);
@ -933,14 +932,14 @@ static void sumo_force_nbp_state(struct radeon_device *rdev)
}
}
static u32 sumo_get_sleep_divider_from_id(u32 id)
u32 sumo_get_sleep_divider_from_id(u32 id)
{
return 1 << id;
}
static u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
u32 sclk,
u32 min_sclk_in_sr)
u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
u32 sclk,
u32 min_sclk_in_sr)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i;
@ -1136,7 +1135,7 @@ int sumo_dpm_enable(struct radeon_device *rdev)
sumo_program_power_level_enter_state(rdev);
sumo_enable_voltage_scaling(rdev, true);
sumo_program_sstp(rdev);
sumo_program_vc(rdev);
sumo_program_vc(rdev, SUMO_VRC_DFLT);
sumo_override_cnb_thermal_events(rdev);
sumo_start_dpm(rdev);
sumo_wait_for_level_0(rdev);
@ -1393,23 +1392,25 @@ static int sumo_parse_power_table(struct radeon_device *rdev)
return 0;
}
static u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, u32 vid_2bit)
u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
struct sumo_vid_mapping_table *vid_mapping_table,
u32 vid_2bit)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i;
for (i = 0; i < pi->sys_info.vid_mapping_table.num_entries; i++) {
if (pi->sys_info.vid_mapping_table.entries[i].vid_2bit == vid_2bit)
return pi->sys_info.vid_mapping_table.entries[i].vid_7bit;
for (i = 0; i < vid_mapping_table->num_entries; i++) {
if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
return vid_mapping_table->entries[i].vid_7bit;
}
return pi->sys_info.vid_mapping_table.entries[pi->sys_info.vid_mapping_table.num_entries - 1].vid_7bit;
return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
}
static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
u32 vid_2bit)
{
u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, vid_2bit);
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
if (vid_7bit > 0x7C)
return 0;
@ -1418,71 +1419,71 @@ static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
}
static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
ATOM_CLK_VOLT_CAPABILITY *table)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i;
for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
if (table[i].ulMaximumSupportedCLK == 0)
break;
pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[i] =
disp_clk_voltage_mapping_table->display_clock_frequency[i] =
table[i].ulMaximumSupportedCLK;
}
pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = i;
disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
if (pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels == 0) {
pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[0] = 80000;
pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = 1;
if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
}
}
static void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
ATOM_AVAILABLE_SCLK_LIST *table)
void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
ATOM_AVAILABLE_SCLK_LIST *table)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i;
u32 n = 0;
u32 prev_sclk = 0;
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
if (table[i].ulSupportedSCLK > prev_sclk) {
pi->sys_info.sclk_voltage_mapping_table.entries[n].sclk_frequency =
sclk_voltage_mapping_table->entries[n].sclk_frequency =
table[i].ulSupportedSCLK;
pi->sys_info.sclk_voltage_mapping_table.entries[n].vid_2bit =
sclk_voltage_mapping_table->entries[n].vid_2bit =
table[i].usVoltageIndex;
prev_sclk = table[i].ulSupportedSCLK;
n++;
}
}
pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries = n;
sclk_voltage_mapping_table->num_max_dpm_entries = n;
}
static void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
ATOM_AVAILABLE_SCLK_LIST *table)
void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
struct sumo_vid_mapping_table *vid_mapping_table,
ATOM_AVAILABLE_SCLK_LIST *table)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i, j;
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
if (table[i].ulSupportedSCLK != 0) {
pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_7bit =
vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
table[i].usVoltageID;
pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_2bit =
vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
table[i].usVoltageIndex;
}
}
for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
if (pi->sys_info.vid_mapping_table.entries[i].vid_7bit == 0) {
if (vid_mapping_table->entries[i].vid_7bit == 0) {
for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
if (pi->sys_info.vid_mapping_table.entries[j].vid_7bit != 0) {
pi->sys_info.vid_mapping_table.entries[i] =
pi->sys_info.vid_mapping_table.entries[j];
pi->sys_info.vid_mapping_table.entries[j].vid_7bit = 0;
if (vid_mapping_table->entries[j].vid_7bit != 0) {
vid_mapping_table->entries[i] =
vid_mapping_table->entries[j];
vid_mapping_table->entries[j].vid_7bit = 0;
break;
}
}
@ -1492,7 +1493,7 @@ static void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
}
}
pi->sys_info.vid_mapping_table.num_entries = i;
vid_mapping_table->num_entries = i;
}
union igp_info {
@ -1561,10 +1562,13 @@ static int sumo_parse_sys_info_table(struct radeon_device *rdev)
else
pi->sys_info.enable_boost = false;
sumo_construct_display_voltage_mapping_table(rdev,
&pi->sys_info.disp_clk_voltage_mapping_table,
igp_info->info_6.sDISPCLK_Voltage);
sumo_construct_sclk_voltage_mapping_table(rdev,
&pi->sys_info.sclk_voltage_mapping_table,
igp_info->info_6.sAvail_SCLK);
sumo_construct_vid_mapping_table(rdev, igp_info->info_6.sAvail_SCLK);
sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
igp_info->info_6.sAvail_SCLK);
}
return 0;

21
drivers/gpu/drm/radeon/sumo_dpm.h
View File

@ -23,6 +23,8 @@
#ifndef __SUMO_DPM_H__
#define __SUMO_DPM_H__
#include "atom.h"
#define SUMO_MAX_HARDWARE_POWERLEVELS 5
#define SUMO_PM_NUMBER_OF_TC 15
@ -184,7 +186,24 @@ struct sumo_power_info {
/* sumo_dpm.c */
u32 sumo_get_xclk(struct radeon_device *rdev);
void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
void sumo_clear_vc(struct radeon_device *rdev);
void sumo_program_sstp(struct radeon_device *rdev);
void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
ATOM_AVAILABLE_SCLK_LIST *table);
void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
struct sumo_vid_mapping_table *vid_mapping_table,
ATOM_AVAILABLE_SCLK_LIST *table);
u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
struct sumo_vid_mapping_table *vid_mapping_table,
u32 vid_2bit);
u32 sumo_get_sleep_divider_from_id(u32 id);
u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
u32 sclk,
u32 min_sclk_in_sr);
/* sumo_smc.c */
void sumo_initialize_m3_arb(struct radeon_device *rdev);

2
drivers/gpu/drm/radeon/sumo_smc.c
View File

@ -21,13 +21,11 @@
*
*/
#include <linux/firmware.h>
#include "drmP.h"
#include "radeon.h"
#include "sumod.h"
#include "sumo_dpm.h"
#include "ppsmc.h"
#include "radeon_ucode.h"
#define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1
#define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27

1613
drivers/gpu/drm/radeon/trinity_dpm.c Normal file
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File diff suppressed because it is too large Load Diff

110
drivers/gpu/drm/radeon/trinity_dpm.h Normal file
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@ -0,0 +1,110 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __TRINITY_DPM_H__
#define __TRINITY_DPM_H__
#include "sumo_dpm.h"
#define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
struct trinity_pl {
u32 sclk;
u8 vddc_index;
u8 ds_divider_index;
u8 ss_divider_index;
u8 allow_gnb_slow;
u8 force_nbp_state;
u8 display_wm;
u8 vce_wm;
};
#define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1 << 0)
#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1)
#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1 << 2)
#define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE (1 << 0)
struct trinity_ps {
u32 num_levels;
struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
u32 nbps_flags;
u32 bapm_flags;
u8 Dpm0PgNbPsLo;
u8 Dpm0PgNbPsHi;
u8 DpmXNbPsLo;
u8 DpmXNbPsHi;
};
#define TRINITY_NUM_NBPSTATES 4
struct trinity_sys_info {
u32 bootup_uma_clk;
u32 bootup_sclk;
u32 min_sclk;
u32 nb_dpm_enable;
u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES];
u16 bootup_nb_voltage_index;
u8 htc_tmp_lmt;
u8 htc_hyst_lmt;
struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
struct sumo_vid_mapping_table vid_mapping_table;
u32 uma_channel_number;
};
struct trinity_power_info {
u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
u32 dpm_interval;
u32 thermal_auto_throttling;
struct trinity_sys_info sys_info;
struct trinity_pl boot_pl;
struct trinity_ps current_ps;
u32 min_sclk_did;
bool enable_nbps_policy;
bool voltage_drop_in_dce;
bool override_dynamic_mgpg;
bool enable_gfx_clock_gating;
bool enable_gfx_power_gating;
bool enable_mg_clock_gating;
bool enable_gfx_dynamic_mgpg;
bool enable_auto_thermal_throttling;
bool enable_dpm;
bool enable_sclk_ds;
};
#define TRINITY_AT_DFLT 30
/* trinity_smc.c */
int trinity_dpm_config(struct radeon_device *rdev, bool enable);
int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
int trinity_dpm_no_forced_level(struct radeon_device *rdev);
int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
bool enable);
int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev);
void trinity_acquire_mutex(struct radeon_device *rdev);
void trinity_release_mutex(struct radeon_device *rdev);
#endif

110
drivers/gpu/drm/radeon/trinity_smc.c Normal file
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@ -0,0 +1,110 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "drmP.h"
#include "radeon.h"
#include "trinityd.h"
#include "trinity_dpm.h"
#include "ppsmc.h"
struct trinity_ps *trinity_get_ps(struct radeon_ps *rps);
struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev);
static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id)
{
int i;
u32 v = 0;
WREG32(SMC_MESSAGE_0, id);
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(SMC_RESP_0) != 0)
break;
udelay(1);
}
v = RREG32(SMC_RESP_0);
if (v != 1) {
if (v == 0xFF) {
DRM_ERROR("SMC failed to handle the message!\n");
return -EINVAL;
} else if (v == 0xFE) {
DRM_ERROR("Unknown SMC message!\n");
return -EINVAL;
}
}
return 0;
}
int trinity_dpm_config(struct radeon_device *rdev, bool enable)
{
if (enable)
WREG32_SMC(SMU_SCRATCH0, 1);
else
WREG32_SMC(SMU_SCRATCH0, 0);
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Config);
}
int trinity_dpm_force_state(struct radeon_device *rdev, u32 n)
{
WREG32_SMC(SMU_SCRATCH0, n);
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DPM_ForceState);
}
int trinity_dpm_no_forced_level(struct radeon_device *rdev)
{
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
}
int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
bool enable)
{
if (enable)
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DCE_AllowVoltageAdjustment);
else
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DCE_RemoveVoltageAdjustment);
}
int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev)
{
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_PG_SIMD_Config);
}
void trinity_acquire_mutex(struct radeon_device *rdev)
{
int i;
WREG32(SMC_INT_REQ, 1);
for (i = 0; i < rdev->usec_timeout; i++) {
if ((RREG32(SMC_INT_REQ) & 0xffff) == 1)
break;
udelay(1);
}
}
void trinity_release_mutex(struct radeon_device *rdev)
{
WREG32(SMC_INT_REQ, 0);
}

223
drivers/gpu/drm/radeon/trinityd.h Normal file
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@ -0,0 +1,223 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Alex Deucher
*/
#ifndef _TRINITYD_H_
#define _TRINITYD_H_
/* pm registers */
/* cg */
#define CG_CGTT_LOCAL_0 0x0
#define CG_CGTT_LOCAL_1 0x1
/* smc */
#define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
# define STATE_VALID(x) ((x) << 0)
# define STATE_VALID_MASK (0xff << 0)
# define STATE_VALID_SHIFT 0
# define CLK_DIVIDER(x) ((x) << 8)
# define CLK_DIVIDER_MASK (0xff << 8)
# define CLK_DIVIDER_SHIFT 8
# define VID(x) ((x) << 16)
# define VID_MASK (0xff << 16)
# define VID_SHIFT 16
# define LVRT(x) ((x) << 24)
# define LVRT_MASK (0xff << 24)
# define LVRT_SHIFT 24
#define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
# define DS_DIV(x) ((x) << 0)
# define DS_DIV_MASK (0xff << 0)
# define DS_DIV_SHIFT 0
# define DS_SH_DIV(x) ((x) << 8)
# define DS_SH_DIV_MASK (0xff << 8)
# define DS_SH_DIV_SHIFT 8
# define DISPLAY_WM(x) ((x) << 16)
# define DISPLAY_WM_MASK (0xff << 16)
# define DISPLAY_WM_SHIFT 16
# define VCE_WM(x) ((x) << 24)
# define VCE_WM_MASK (0xff << 24)
# define VCE_WM_SHIFT 24
#define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c
# define GNB_SLOW(x) ((x) << 0)
# define GNB_SLOW_MASK (0xff << 0)
# define GNB_SLOW_SHIFT 0
# define FORCE_NBPS1(x) ((x) << 8)
# define FORCE_NBPS1_MASK (0xff << 8)
# define FORCE_NBPS1_SHIFT 8
#define SMU_SCLK_DPM_STATE_0_AT 0x1f010
# define AT(x) ((x) << 0)
# define AT_MASK (0xff << 0)
# define AT_SHIFT 0
#define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014
# define PD_SCLK_DIVIDER(x) ((x) << 16)
# define PD_SCLK_DIVIDER_MASK (0xff << 16)
# define PD_SCLK_DIVIDER_SHIFT 16
#define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020
#define SMU_SCLK_DPM_CNTL 0x1f100
# define SCLK_DPM_EN(x) ((x) << 0)
# define SCLK_DPM_EN_MASK (0xff << 0)
# define SCLK_DPM_EN_SHIFT 0
# define SCLK_DPM_BOOT_STATE(x) ((x) << 16)
# define SCLK_DPM_BOOT_STATE_MASK (0xff << 16)
# define SCLK_DPM_BOOT_STATE_SHIFT 16
# define VOLTAGE_CHG_EN(x) ((x) << 24)
# define VOLTAGE_CHG_EN_MASK (0xff << 24)
# define VOLTAGE_CHG_EN_SHIFT 24
#define SMU_SCLK_DPM_TT_CNTL 0x1f108
# define SCLK_TT_EN(x) ((x) << 0)
# define SCLK_TT_EN_MASK (0xff << 0)
# define SCLK_TT_EN_SHIFT 0
#define SMU_SCLK_DPM_TTT 0x1f10c
# define LT(x) ((x) << 0)
# define LT_MASK (0xffff << 0)
# define LT_SHIFT 0
# define HT(x) ((x) << 16)
# define HT_MASK (0xffff << 16)
# define HT_SHIFT 16
#define SMU_S_PG_CNTL 0x1f118
# define DS_PG_EN(x) ((x) << 16)
# define DS_PG_EN_MASK (0xff << 16)
# define DS_PG_EN_SHIFT 16
#define GFX_POWER_GATING_CNTL 0x1f38c
# define PDS_DIV(x) ((x) << 0)
# define PDS_DIV_MASK (0xff << 0)
# define PDS_DIV_SHIFT 0
# define SSSD(x) ((x) << 8)
# define SSSD_MASK (0xff << 8)
# define SSSD_SHIFT 8
#define PM_CONFIG 0x1f428
# define SVI_Mode (1 << 29)
#define PM_I_CNTL_1 0x1f464
# define SCLK_DPM(x) ((x) << 0)
# define SCLK_DPM_MASK (0xff << 0)
# define SCLK_DPM_SHIFT 0
# define DS_PG_CNTL(x) ((x) << 16)
# define DS_PG_CNTL_MASK (0xff << 16)
# define DS_PG_CNTL_SHIFT 16
#define PM_TP 0x1f468
#define NB_PSTATE_CONFIG 0x1f5f8
# define Dpm0PgNbPsLo(x) ((x) << 0)
# define Dpm0PgNbPsLo_MASK (3 << 0)
# define Dpm0PgNbPsLo_SHIFT 0
# define Dpm0PgNbPsHi(x) ((x) << 2)
# define Dpm0PgNbPsHi_MASK (3 << 2)
# define Dpm0PgNbPsHi_SHIFT 2
# define DpmXNbPsLo(x) ((x) << 4)
# define DpmXNbPsLo_MASK (3 << 4)
# define DpmXNbPsLo_SHIFT 4
# define DpmXNbPsHi(x) ((x) << 6)
# define DpmXNbPsHi_MASK (3 << 6)
# define DpmXNbPsHi_SHIFT 6
#define DC_CAC_VALUE 0x1f908
#define GPU_CAC_AVRG_CNTL 0x1f920
# define WINDOW_SIZE(x) ((x) << 0)
# define WINDOW_SIZE_MASK (0xff << 0)
# define WINDOW_SIZE_SHIFT 0
#define CC_SMU_MISC_FUSES 0xe0001004
# define MinSClkDid(x) ((x) << 2)
# define MinSClkDid_MASK (0x7f << 2)
# define MinSClkDid_SHIFT 2
#define CC_SMU_TST_EFUSE1_MISC 0xe000101c
# define RB_BACKEND_DISABLE(x) ((x) << 16)
# define RB_BACKEND_DISABLE_MASK (3 << 16)
# define RB_BACKEND_DISABLE_SHIFT 16
#define SMU_SCRATCH_A 0xe0003024
#define SMU_SCRATCH0 0xe0003040
/* mmio */
#define SMC_INT_REQ 0x220
#define SMC_MESSAGE_0 0x22c
#define SMC_RESP_0 0x230
#define GENERAL_PWRMGT 0x670
# define GLOBAL_PWRMGT_EN (1 << 0)
#define SCLK_PWRMGT_CNTL 0x678
# define DYN_PWR_DOWN_EN (1 << 2)
# define RESET_BUSY_CNT (1 << 4)
# define RESET_SCLK_CNT (1 << 5)
# define DYN_GFX_CLK_OFF_EN (1 << 7)
# define GFX_CLK_FORCE_ON (1 << 8)
# define DYNAMIC_PM_EN (1 << 21)
#define TARGET_AND_CURRENT_PROFILE_INDEX 0x684
# define TARGET_STATE(x) ((x) << 0)
# define TARGET_STATE_MASK (0xf << 0)
# define TARGET_STATE_SHIFT 0
# define CURRENT_STATE(x) ((x) << 4)
# define CURRENT_STATE_MASK (0xf << 4)
# define CURRENT_STATE_SHIFT 4
#define CG_GIPOTS 0x6d8
# define CG_GIPOT(x) ((x) << 16)
# define CG_GIPOT_MASK (0xffff << 16)
# define CG_GIPOT_SHIFT 16
#define CG_PG_CTRL 0x6e0
# define SP(x) ((x) << 0)
# define SP_MASK (0xffff << 0)
# define SP_SHIFT 0
# define SU(x) ((x) << 16)
# define SU_MASK (0xffff << 16)
# define SU_SHIFT 16
#define CG_THERMAL_INT_CTRL 0x738
# define DIG_THERM_INTH(x) ((x) << 0)
# define DIG_THERM_INTH_MASK (0xff << 0)
# define DIG_THERM_INTH_SHIFT 0
# define DIG_THERM_INTL(x) ((x) << 8)
# define DIG_THERM_INTL_MASK (0xff << 8)
# define DIG_THERM_INTL_SHIFT 8
# define THERM_INTH_MASK (1 << 24)
# define THERM_INTL_MASK (1 << 25)
#define CG_CG_VOLTAGE_CNTL 0x770
# define EN (1 << 9)
#define HW_REV 0x5564
# define ATI_REV_ID_MASK (0xf << 28)
# define ATI_REV_ID_SHIFT 28
/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
#define CGTS_SM_CTRL_REG 0x9150
#define GB_ADDR_CONFIG 0x98f8
#endif