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drm/i915: Limit the watermark to at least 8 entries on gen2/3
830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO). Limit the watermark value to at least 8 cache lines. That also matches the burst size we use on most platforms. BSpec seems to indicate we should limit the watermark to 'burst size + 1'. But on gen4 we already use a hardcoded 8 as the watermark value (as the spec says we should), so just use 8 as the limit on gen2/3 as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1070,6 +1070,17 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
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wm_size = wm->max_wm;
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if (wm_size <= 0)
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wm_size = wm->default_wm;
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/*
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* Bspec seems to indicate that the value shouldn't be lower than
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* 'burst size + 1'. Certainly 830 is quite unhappy with low values.
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* Lets go for 8 which is the burst size since certain platforms
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* already use a hardcoded 8 (which is what the spec says should be
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* done).
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*/
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if (wm_size <= 8)
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wm_size = 8;
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return wm_size;
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}
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