arch/tile: update some comments to clarify register usage.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf 2010-10-14 14:42:58 -04:00
parent 5592840ba8
commit d6f0f22c3c
2 changed files with 6 additions and 3 deletions

View File

@ -1553,6 +1553,8 @@ STD_ENTRY(_sys_clone)
* to be available to it on entry. It does not modify any callee-save
* registers (including "lr"). It does not check what PL it is being
* called at, so you'd better not call it other than at PL0.
* The <atomic.h> wrapper assumes it only clobbers r20-r29, so if
* it ever is necessary to use more registers, be aware.
*
* It does not use the stack, but since it might be re-interrupted by
* a page fault which would assume the stack was valid, it does

View File

@ -214,9 +214,10 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
/*
* Copy the callee-saved registers from the passed pt_regs struct
* into the context-switch callee-saved registers area.
* We have to restore the callee-saved registers since we may
* be cloning a userspace task with userspace register state,
* and we won't be unwinding the same kernel frames to restore them.
* This way when we start the interrupt-return sequence, the
* callee-save registers will be correctly in registers, which
* is how we assume the compiler leaves them as we start doing
* the normal return-from-interrupt path after calling C code.
* Zero out the C ABI save area to mark the top of the stack.
*/
ksp = (unsigned long) childregs;