Merge series "spi: Set of cleanups" from Jay Fang <f.fangjian@huawei.com>:

Some cleanups of SPI drivers. No functional change.

Thanks,
Jay

Jay Fang (4):
  spi: ppc4xx: include <linux/io.h> instead of <asm/io.h>
  spi: omap-100k: Clean the value of 'status' is not used
  spi: delete repeated words in comments
  spi: spi-loopback-test: Fix 'tx_buf' might be 'rx_buf'

 drivers/spi/spi-bcm2835aux.c    | 2 +-
 drivers/spi/spi-dw-mmio.c       | 2 +-
 drivers/spi/spi-geni-qcom.c     | 4 ++--
 drivers/spi/spi-loopback-test.c | 2 +-
 drivers/spi/spi-omap-100k.c     | 2 --
 drivers/spi/spi-pl022.c         | 4 ++--
 drivers/spi/spi-ppc4xx.c        | 4 ++--
 7 files changed, 9 insertions(+), 11 deletions(-)

--
2.7.4
This commit is contained in:
Mark Brown 2021-05-11 09:06:07 +01:00
commit d6e58e3796
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
7 changed files with 9 additions and 11 deletions

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@ -384,7 +384,7 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
bs->pending = 0;
/* Calculate the estimated time in us the transfer runs. Note that
* there are are 2 idle clocks cycles after each chunk getting
* there are 2 idle clocks cycles after each chunk getting
* transferred - in our case the chunk size is 3 bytes, so we
* approximate this by 9 cycles/byte. This is used to find the number
* of Hz per byte per polling limit. E.g., we can transfer 1 byte in

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@ -56,7 +56,7 @@ struct dw_spi_mscc {
/*
* The Designware SPI controller (referred to as master in the documentation)
* automatically deasserts chip select when the tx fifo is empty. The chip
* selects then needs to be either driven as GPIOs or, for the first 4 using the
* selects then needs to be either driven as GPIOs or, for the first 4 using
* the SPI boot controller registers. the final chip select is an OR gate
* between the Designware SPI controller and the SPI boot controller.
*/

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@ -639,8 +639,8 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
complete(&mas->abort_done);
/*
* It's safe or a good idea to Ack all of our our interrupts at the
* end of the function. Specifically:
* It's safe or a good idea to Ack all of our interrupts at the end
* of the function. Specifically:
* - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
* clearing Acks. Clearing at the end relies on nobody else having
* started a new transfer yet or else we could be clearing _their_

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@ -875,7 +875,7 @@ static int spi_test_run_iter(struct spi_device *spi,
test.transfers[i].len = len;
if (test.transfers[i].tx_buf)
test.transfers[i].tx_buf += tx_off;
if (test.transfers[i].tx_buf)
if (test.transfers[i].rx_buf)
test.transfers[i].rx_buf += rx_off;
}

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@ -296,7 +296,6 @@ static int omap1_spi100k_transfer_one_message(struct spi_master *master,
list_for_each_entry(t, &m->transfers, transfer_list) {
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
status = -EINVAL;
break;
}
status = omap1_spi100k_setup_transfer(spi, t);
@ -315,7 +314,6 @@ static int omap1_spi100k_transfer_one_message(struct spi_master *master,
m->actual_length += count;
if (count != t->len) {
status = -EIO;
break;
}
}

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@ -288,7 +288,7 @@
#define SPI_POLLING_TIMEOUT 1000
/*
* The type of reading going on on this chip
* The type of reading going on this chip
*/
enum ssp_reading {
READING_NULL,
@ -298,7 +298,7 @@ enum ssp_reading {
};
/*
* The type of writing going on on this chip
* The type of writing going on this chip
*/
enum ssp_writing {
WRITING_NULL,

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@ -34,7 +34,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <asm/io.h>
#include <linux/io.h>
#include <asm/dcr.h>
#include <asm/dcr-regs.h>
@ -326,7 +326,7 @@ static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
{
/*
* On all 4xx PPC's the SPI bus is shared/multiplexed with
* the 2nd I2C bus. We need to enable the the SPI bus before
* the 2nd I2C bus. We need to enable the SPI bus before
* using it.
*/