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Merge series "spi: Set of cleanups" from Jay Fang <f.fangjian@huawei.com>:
Some cleanups of SPI drivers. No functional change. Thanks, Jay Jay Fang (4): spi: ppc4xx: include <linux/io.h> instead of <asm/io.h> spi: omap-100k: Clean the value of 'status' is not used spi: delete repeated words in comments spi: spi-loopback-test: Fix 'tx_buf' might be 'rx_buf' drivers/spi/spi-bcm2835aux.c | 2 +- drivers/spi/spi-dw-mmio.c | 2 +- drivers/spi/spi-geni-qcom.c | 4 ++-- drivers/spi/spi-loopback-test.c | 2 +- drivers/spi/spi-omap-100k.c | 2 -- drivers/spi/spi-pl022.c | 4 ++-- drivers/spi/spi-ppc4xx.c | 4 ++-- 7 files changed, 9 insertions(+), 11 deletions(-) -- 2.7.4
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d6e58e3796
@ -384,7 +384,7 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
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bs->pending = 0;
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/* Calculate the estimated time in us the transfer runs. Note that
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* there are are 2 idle clocks cycles after each chunk getting
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* there are 2 idle clocks cycles after each chunk getting
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* transferred - in our case the chunk size is 3 bytes, so we
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* approximate this by 9 cycles/byte. This is used to find the number
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* of Hz per byte per polling limit. E.g., we can transfer 1 byte in
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@ -56,7 +56,7 @@ struct dw_spi_mscc {
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/*
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* The Designware SPI controller (referred to as master in the documentation)
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* automatically deasserts chip select when the tx fifo is empty. The chip
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* selects then needs to be either driven as GPIOs or, for the first 4 using the
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* selects then needs to be either driven as GPIOs or, for the first 4 using
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* the SPI boot controller registers. the final chip select is an OR gate
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* between the Designware SPI controller and the SPI boot controller.
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*/
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@ -639,8 +639,8 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
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complete(&mas->abort_done);
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/*
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* It's safe or a good idea to Ack all of our our interrupts at the
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* end of the function. Specifically:
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* It's safe or a good idea to Ack all of our interrupts at the end
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* of the function. Specifically:
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* - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
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* clearing Acks. Clearing at the end relies on nobody else having
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* started a new transfer yet or else we could be clearing _their_
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@ -875,7 +875,7 @@ static int spi_test_run_iter(struct spi_device *spi,
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test.transfers[i].len = len;
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if (test.transfers[i].tx_buf)
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test.transfers[i].tx_buf += tx_off;
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if (test.transfers[i].tx_buf)
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if (test.transfers[i].rx_buf)
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test.transfers[i].rx_buf += rx_off;
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}
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@ -296,7 +296,6 @@ static int omap1_spi100k_transfer_one_message(struct spi_master *master,
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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status = -EINVAL;
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break;
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}
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status = omap1_spi100k_setup_transfer(spi, t);
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@ -315,7 +314,6 @@ static int omap1_spi100k_transfer_one_message(struct spi_master *master,
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m->actual_length += count;
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if (count != t->len) {
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status = -EIO;
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break;
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}
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}
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@ -288,7 +288,7 @@
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#define SPI_POLLING_TIMEOUT 1000
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/*
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* The type of reading going on on this chip
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* The type of reading going on this chip
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*/
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enum ssp_reading {
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READING_NULL,
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@ -298,7 +298,7 @@ enum ssp_reading {
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};
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/*
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* The type of writing going on on this chip
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* The type of writing going on this chip
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*/
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enum ssp_writing {
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WRITING_NULL,
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@ -34,7 +34,7 @@
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <asm/io.h>
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#include <linux/io.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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@ -326,7 +326,7 @@ static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
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{
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/*
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* On all 4xx PPC's the SPI bus is shared/multiplexed with
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* the 2nd I2C bus. We need to enable the the SPI bus before
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* the 2nd I2C bus. We need to enable the SPI bus before
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* using it.
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*/
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