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parisc: Enable TOC (transfer of contents) feature unconditionally
Before this patch, the TOC code used a pre-allocated stack of 16kb for each possible CPU. That space overhead was the reason why the TOC feature wasn't enabled by default for 32-bit kernels. This patch rewrites the TOC code to use a per-cpu stack. That way we use much less memory now and as such we enable the TOC feature by default on all kernels. Additionally the dump of the registers and the stacktrace wasn't serialized, which led to multiple CPUs printing the stack backtrace at once which rendered the output unreadable. Now the backtraces are nicely serialized by a lock. Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller
parent
6968e707d3
commit
d6ab9fc745
@ -287,20 +287,6 @@ config SMP
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If you don't know what to do here, say N.
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config TOC
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bool "Support TOC switch"
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default y if 64BIT || !SMP
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help
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Most PA-RISC machines have either a switch at the back of the machine
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or a command in BMC to trigger a TOC interrupt. If you say Y here a
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handler will be installed which will either show a backtrace on all
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CPUs, or enter a possible configured debugger like kgdb/kdb.
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Note that with this option enabled, the kernel will use an additional 16KB
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per possible CPU as a special stack for the TOC handler.
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If you don't want to debug the Kernel, say N.
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config PARISC_CPU_TOPOLOGY
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bool "Support cpu topology definition"
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depends on SMP
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@ -10,7 +10,7 @@ obj-y := cache.o pacache.o setup.o pdt.o traps.o time.o irq.o \
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ptrace.o hardware.o inventory.o drivers.o alternative.o \
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signal.o hpmc.o real2.o parisc_ksyms.o unaligned.o \
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process.o processor.o pdc_cons.o pdc_chassis.o unwind.o \
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patch.o
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patch.o toc.o toc_asm.o
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ifdef CONFIG_FUNCTION_TRACER
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# Do not profile debug and lowlevel utilities
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@ -39,4 +39,3 @@ obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_KPROBES) += kprobes.o
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obj-$(CONFIG_KEXEC_CORE) += kexec.o relocate_kernel.o
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obj-$(CONFIG_KEXEC_FILE) += kexec_file.o
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obj-$(CONFIG_TOC) += toc.o toc_asm.o
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@ -36,6 +36,9 @@
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int main(void)
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{
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DEFINE(TASK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
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#ifdef CONFIG_SMP
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DEFINE(TASK_TI_CPU, offsetof(struct task_struct, thread_info.cpu));
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#endif
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DEFINE(TASK_STACK, offsetof(struct task_struct, stack));
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DEFINE(TASK_PAGEFAULT_DISABLED, offsetof(struct task_struct, pagefault_disabled));
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BLANK();
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@ -9,8 +9,10 @@
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#include <asm/pdc.h>
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#include <asm/pdc_chassis.h>
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#include <asm/ldcw.h>
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unsigned int __aligned(16) toc_lock = 1;
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static unsigned int __aligned(16) toc_lock = 1;
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DEFINE_PER_CPU_PAGE_ALIGNED(char [16384], toc_stack);
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static void toc20_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_20 *toc)
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{
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@ -63,7 +65,8 @@ void notrace __noreturn __cold toc_intr(struct pt_regs *regs)
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struct pdc_toc_pim_20 pim_data20;
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struct pdc_toc_pim_11 pim_data11;
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nmi_enter();
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/* verify we wrote regs to the correct stack */
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BUG_ON(regs != (struct pt_regs *)&per_cpu(toc_stack, raw_smp_processor_id()));
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if (boot_cpu_data.cpu_type >= pcxu) {
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if (pdc_pim_toc20(&pim_data20))
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@ -76,14 +79,25 @@ void notrace __noreturn __cold toc_intr(struct pt_regs *regs)
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}
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#ifdef CONFIG_KGDB
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nmi_enter();
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if (atomic_read(&kgdb_active) != -1)
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kgdb_nmicallback(raw_smp_processor_id(), regs);
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kgdb_handle_exception(9, SIGTRAP, 0, regs);
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#endif
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/* serialize output, otherwise all CPUs write backtrace at once */
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while (__ldcw(&toc_lock) == 0)
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; /* wait */
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show_regs(regs);
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toc_lock = 1; /* release lock for next CPU */
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if (raw_smp_processor_id() != 0)
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while (1) ; /* all but monarch CPU will wait endless. */
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/* give other CPUs time to show their backtrace */
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mdelay(2000);
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machine_restart("TOC");
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/* should never reach this */
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@ -5,34 +5,25 @@
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.level 1.1
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#include <asm/assembly.h>
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#include <asm/psw.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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.text
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.import toc_intr,code
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.import toc_lock,data
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.import toc_stack,data
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.align 16
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ENTRY_CFI(toc_handler)
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/*
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* synchronize CPUs and obtain offset
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* for stack setup.
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*/
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load32 PA(toc_lock),%r1
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0: ldcw,co 0(%r1),%r2
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cmpib,= 0,%r2,0b
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nop
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addi 1,%r2,%r4
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stw %r4,0(%r1)
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addi -1,%r2,%r4
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load32 PA(toc_stack),%sp
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/*
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* deposit CPU number into stack address,
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* so every CPU will have its own stack.
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*/
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SHLREG %r4,14,%r4
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#ifdef CONFIG_SMP
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/* get per-cpu toc_stack address. */
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mfctl %cr30, %r1
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tophys %r1,%r2 /* task_struct */
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LDREG TASK_TI_CPU(%r2),%r4 /* cpu */
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load32 PA(__per_cpu_offset),%r1
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LDREGX %r4(%r1),%r4
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add %r4,%sp,%sp
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#endif
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/*
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* setup pt_regs on stack and save the
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@ -82,7 +73,3 @@ ENDPROC_CFI(toc_handler)
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*/
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SYM_DATA(toc_handler_csum, .long 0)
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SYM_DATA(toc_handler_size, .long . - toc_handler)
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__PAGE_ALIGNED_BSS
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.align 64
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SYM_DATA(toc_stack, .block 16384*NR_CPUS)
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