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tty: serial: sh-sci: Add support for tx end interrupt handling
As per the RZ/G2L users hardware manual (Rev.1.20 Sep, 2022), section 23.3.7 Serial Data Transmission (Asynchronous Mode), it is mentioned that, set the SCR.TIE bit to 0 and SCR.TEIE bit to 1, after the last data to be transmitted are written to the TDR. This will generate tx end interrupt and in the handler set SCR.TE and SCR.TEIE to 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230412145053.114847-5-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -860,9 +860,16 @@ static void sci_transmit_chars(struct uart_port *port)
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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sci_stop_tx(port);
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if (uart_circ_empty(xmit)) {
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if (port->type == PORT_SCI) {
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ctrl = serial_port_in(port, SCSCR);
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ctrl &= ~SCSCR_TIE;
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ctrl |= SCSCR_TEIE;
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serial_port_out(port, SCSCR, ctrl);
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}
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sci_stop_tx(port);
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}
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}
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static void sci_receive_chars(struct uart_port *port)
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@ -1766,6 +1773,24 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
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return IRQ_HANDLED;
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}
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static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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unsigned long flags;
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unsigned short ctrl;
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if (port->type != PORT_SCI)
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return sci_tx_interrupt(irq, ptr);
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spin_lock_irqsave(&port->lock, flags);
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ctrl = serial_port_in(port, SCSCR);
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ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
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serial_port_out(port, SCSCR, ctrl);
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spin_unlock_irqrestore(&port->lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t sci_br_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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@ -1902,7 +1927,7 @@ static const struct sci_irq_desc {
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[SCIx_TEI_IRQ] = {
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.desc = "tx end",
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.handler = sci_tx_interrupt,
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.handler = sci_tx_end_interrupt,
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},
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/*
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@ -59,6 +59,9 @@ enum {
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#define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
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#define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
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/* Serial Control Register, SCI only bits */
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#define SCSCR_TEIE BIT(2) /* Transmit End Interrupt Enable */
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/* Serial Control Register, SCIFA/SCIFB only bits */
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#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
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