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Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
This reverts commit e721295185
.
The code changes the flags of the wrong cpus - which breaks the whole
bootup of secondary CPUs.
Cc: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
This commit is contained in:
parent
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@ -41,6 +41,9 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)0xf0000000;
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}
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static DEFINE_SPINLOCK(scu_lock);
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static unsigned long tmp;
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
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void __init sh73a0_register_twd(void)
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@ -49,6 +52,20 @@ void __init sh73a0_register_twd(void)
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}
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#endif
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static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
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{
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void __iomem *scu_base = scu_base_addr();
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spin_lock(&scu_lock);
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tmp = __raw_readl(scu_base + 8);
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tmp &= ~clr;
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tmp |= set;
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spin_unlock(&scu_lock);
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/* disable cache coherency after releasing the lock */
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__raw_writel(tmp, scu_base + 8);
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}
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static unsigned int __init sh73a0_get_core_count(void)
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{
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void __iomem *scu_base = scu_base_addr();
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@ -66,7 +83,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
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cpu = cpu_logical_map(cpu);
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/* enable cache coherency */
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scu_power_mode(scu_base_addr(), 0);
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, WUPCR); /* wake up */
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@ -78,6 +95,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
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static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu = cpu_logical_map(0);
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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@ -85,7 +104,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
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__raw_writel(__pa(shmobile_secondary_vector), SBAR);
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/* enable cache coherency on CPU0 */
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scu_power_mode(scu_base_addr(), 0);
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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}
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static void __init sh73a0_smp_init_cpus(void)
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