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Merge remote-tracking branches 'regulator/topic/lp8755', 'regulator/topic/ltc3589', 'regulator/topic/max8952', 'regulator/topic/mc13xxx' and 'regulator/topic/palmas' into regulator-next

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This commit is contained in:
Mark Brown 2014-08-05 18:29:24 +01:00
commit d5b5d9d43b
10 changed files with 1867 additions and 467 deletions
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2
Documentation/devicetree/bindings/mfd/palmas.txt
View File

@ -6,6 +6,7 @@ twl6037 (palmas)
tps65913 (palmas)
tps65914 (palmas)
tps659038
tps65917
Required properties:
- compatible : Should be from the list
@ -16,6 +17,7 @@ Required properties:
ti,tps65914
ti,tps80036
ti,tps659038
ti,tps65917
and also the generic series names
ti,palmas
- interrupt-controller : palmas has its own internal IRQs

1
Documentation/devicetree/bindings/regulator/palmas-pmic.txt
View File

@ -7,6 +7,7 @@ Required properties:
ti,twl6037-pmic
ti,tps65913-pmic
ti,tps65914-pmic
ti,tps65917-pmic
and also the generic series names
ti,palmas-pmic
- interrupt-parent : The parent interrupt controller which is palmas.

233
drivers/mfd/palmas.c
View File

@ -25,52 +25,6 @@
#include <linux/mfd/palmas.h>
#include <linux/of_device.h>
#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
PALMAS_EXT_CONTROL_ENABLE2 | \
PALMAS_EXT_CONTROL_NSLEEP)
struct palmas_sleep_requestor_info {
int id;
int reg_offset;
int bit_pos;
};
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
.reg_offset = _offset, \
.bit_pos = _pos, \
}
static struct palmas_sleep_requestor_info sleep_req_info[] = {
EXTERNAL_REQUESTOR(REGEN1, 0, 0),
EXTERNAL_REQUESTOR(REGEN2, 0, 1),
EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
EXTERNAL_REQUESTOR(REGEN3, 0, 6),
EXTERNAL_REQUESTOR(SMPS12, 1, 0),
EXTERNAL_REQUESTOR(SMPS3, 1, 1),
EXTERNAL_REQUESTOR(SMPS45, 1, 2),
EXTERNAL_REQUESTOR(SMPS6, 1, 3),
EXTERNAL_REQUESTOR(SMPS7, 1, 4),
EXTERNAL_REQUESTOR(SMPS8, 1, 5),
EXTERNAL_REQUESTOR(SMPS9, 1, 6),
EXTERNAL_REQUESTOR(SMPS10, 1, 7),
EXTERNAL_REQUESTOR(LDO1, 2, 0),
EXTERNAL_REQUESTOR(LDO2, 2, 1),
EXTERNAL_REQUESTOR(LDO3, 2, 2),
EXTERNAL_REQUESTOR(LDO4, 2, 3),
EXTERNAL_REQUESTOR(LDO5, 2, 4),
EXTERNAL_REQUESTOR(LDO6, 2, 5),
EXTERNAL_REQUESTOR(LDO7, 2, 6),
EXTERNAL_REQUESTOR(LDO8, 2, 7),
EXTERNAL_REQUESTOR(LDO9, 3, 0),
EXTERNAL_REQUESTOR(LDOLN, 3, 1),
EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
};
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
@ -92,6 +46,133 @@ static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
},
};
static const struct regmap_irq tps65917_irqs[] = {
/* INT1 IRQs */
[TPS65917_RESERVED1] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRON_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRON,
},
[TPS65917_LONG_PRESS_KEY_IRQ] = {
.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
},
[TPS65917_RESERVED2] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRDOWN_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRDOWN,
},
[TPS65917_HOTDIE_IRQ] = {
.mask = TPS65917_INT1_STATUS_HOTDIE,
},
[TPS65917_VSYS_MON_IRQ] = {
.mask = TPS65917_INT1_STATUS_VSYS_MON,
},
[TPS65917_RESERVED3] = {
.mask = TPS65917_RESERVED,
},
/* INT2 IRQs*/
[TPS65917_RESERVED4] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_OTP_ERROR_IRQ] = {
.mask = TPS65917_INT2_STATUS_OTP_ERROR,
.reg_offset = 1,
},
[TPS65917_WDT_IRQ] = {
.mask = TPS65917_INT2_STATUS_WDT,
.reg_offset = 1,
},
[TPS65917_RESERVED5] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_RESET_IN_IRQ] = {
.mask = TPS65917_INT2_STATUS_RESET_IN,
.reg_offset = 1,
},
[TPS65917_FSD_IRQ] = {
.mask = TPS65917_INT2_STATUS_FSD,
.reg_offset = 1,
},
[TPS65917_SHORT_IRQ] = {
.mask = TPS65917_INT2_STATUS_SHORT,
.reg_offset = 1,
},
[TPS65917_RESERVED6] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
/* INT3 IRQs */
[TPS65917_GPADC_AUTO_0_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
.reg_offset = 2,
},
[TPS65917_GPADC_AUTO_1_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
.reg_offset = 2,
},
[TPS65917_GPADC_EOC_SW_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
.reg_offset = 2,
},
[TPS65917_RESREVED6] = {
.mask = TPS65917_RESERVED6,
.reg_offset = 2,
},
[TPS65917_RESERVED7] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED8] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED9] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_VBUS_IRQ] = {
.mask = TPS65917_INT3_STATUS_VBUS,
.reg_offset = 2,
},
/* INT4 IRQs */
[TPS65917_GPIO_0_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_0,
.reg_offset = 3,
},
[TPS65917_GPIO_1_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_1,
.reg_offset = 3,
},
[TPS65917_GPIO_2_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_2,
.reg_offset = 3,
},
[TPS65917_GPIO_3_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_3,
.reg_offset = 3,
},
[TPS65917_GPIO_4_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_4,
.reg_offset = 3,
},
[TPS65917_GPIO_5_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_5,
.reg_offset = 3,
},
[TPS65917_GPIO_6_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_6,
.reg_offset = 3,
},
[TPS65917_RESERVED10] = {
.mask = TPS65917_RESERVED10,
.reg_offset = 3,
},
};
static const struct regmap_irq palmas_irqs[] = {
/* INT1 IRQs */
[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
@ -232,13 +313,26 @@ static struct regmap_irq_chip palmas_irq_chip = {
PALMAS_INT1_MASK),
};
static struct regmap_irq_chip tps65917_irq_chip = {
.name = "tps65917",
.irqs = tps65917_irqs,
.num_irqs = ARRAY_SIZE(tps65917_irqs),
.num_regs = 4,
.irq_reg_stride = 5,
.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_STATUS),
.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_MASK),
};
int palmas_ext_control_req_config(struct palmas *palmas,
enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
{
struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
int preq_mask_bit = 0;
int reg_add = 0;
int bit_pos;
int ret;
int bit_pos, ret;
if (!(ext_ctrl & PALMAS_EXT_REQ))
return 0;
@ -257,8 +351,8 @@ int palmas_ext_control_req_config(struct palmas *palmas,
preq_mask_bit = 2;
}
bit_pos = sleep_req_info[id].bit_pos;
reg_add += sleep_req_info[id].reg_offset;
bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
if (enable)
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
reg_add, BIT(bit_pos), BIT(bit_pos));
@ -357,14 +451,38 @@ static void palmas_power_off(void)
static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
static unsigned int tps659038_features;
struct palmas_driver_data {
unsigned int *features;
struct regmap_irq_chip *irq_chip;
};
static struct palmas_driver_data palmas_data = {
.features = &palmas_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps659038_data = {
.features = &tps659038_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps65917_data = {
.features = &tps659038_features,
.irq_chip = &tps65917_irq_chip,
};
static const struct of_device_id of_palmas_match_tbl[] = {
{
.compatible = "ti,palmas",
.data = &palmas_features,
.data = &palmas_data,
},
{
.compatible = "ti,tps659038",
.data = &tps659038_features,
.data = &tps659038_data,
},
{
.compatible = "ti,tps65917",
.data = &tps65917_data,
},
{ },
};
@ -375,9 +493,10 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
{
struct palmas *palmas;
struct palmas_platform_data *pdata;
struct palmas_driver_data *driver_data;
struct device_node *node = i2c->dev.of_node;
int ret = 0, i;
unsigned int reg, addr, *features;
unsigned int reg, addr;
int slave;
const struct of_device_id *match;
@ -408,8 +527,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
if (!match)
return -ENODATA;
features = (unsigned int *)match->data;
palmas->features = *features;
driver_data = (struct palmas_driver_data *)match->data;
palmas->features = *driver_data->features;
for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
if (i == 0)
@ -463,8 +582,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
regmap_write(palmas->regmap[slave], addr, reg);
ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
IRQF_ONESHOT | pdata->irq_flags, 0, &palmas_irq_chip,
&palmas->irq_data);
IRQF_ONESHOT | pdata->irq_flags, 0,
driver_data->irq_chip, &palmas->irq_data);
if (ret < 0)
goto err_i2c;

23
drivers/regulator/lp8755.c
View File

@ -339,22 +339,18 @@ static int lp8755_regulator_init(struct lp8755_chip *pchip)
rconfig.init_data = pdata->buck_data[buck_num];
rconfig.of_node = pchip->dev->of_node;
pchip->rdev[buck_num] =
regulator_register(&lp8755_regulators[buck_num], &rconfig);
devm_regulator_register(pchip->dev,
&lp8755_regulators[buck_num], &rconfig);
if (IS_ERR(pchip->rdev[buck_num])) {
ret = PTR_ERR(pchip->rdev[buck_num]);
pchip->rdev[buck_num] = NULL;
dev_err(pchip->dev, "regulator init failed: buck %d\n",
buck_num);
goto err_buck;
return ret;
}
}
return 0;
err_buck:
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
regulator_unregister(pchip->rdev[icnt]);
return ret;
}
static irqreturn_t lp8755_irq_handler(int irq, void *data)
@ -490,23 +486,19 @@ static int lp8755_probe(struct i2c_client *client,
ret = lp8755_regulator_init(pchip);
if (ret < 0) {
dev_err(&client->dev, "fail to initialize regulators\n");
goto err_regulator;
goto err;
}
pchip->irq = client->irq;
ret = lp8755_int_config(pchip);
if (ret < 0) {
dev_err(&client->dev, "fail to irq config\n");
goto err_irq;
goto err;
}
return ret;
err_irq:
for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
regulator_unregister(pchip->rdev[icnt]);
err_regulator:
err:
/* output disable */
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
lp8755_write(pchip, icnt, 0x00);
@ -519,9 +511,6 @@ static int lp8755_remove(struct i2c_client *client)
int icnt;
struct lp8755_chip *pchip = i2c_get_clientdata(client);
for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
regulator_unregister(pchip->rdev[icnt]);
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
lp8755_write(pchip, icnt, 0x00);

2
drivers/regulator/ltc3589.c
View File

@ -377,7 +377,7 @@ static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
return false;
}
struct reg_default ltc3589_reg_defaults[] = {
static struct reg_default ltc3589_reg_defaults[] = {
{ LTC3589_SCR1, 0x00 },
{ LTC3589_OVEN, 0x00 },
{ LTC3589_SCR2, 0x00 },

34
drivers/regulator/max8952.c
View File

@ -229,7 +229,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
config.ena_gpio_flags |= GPIOF_OUT_INIT_HIGH;
rdev = devm_regulator_register(&client->dev, &regulator, &config);
if (IS_ERR(rdev)) {
ret = PTR_ERR(rdev);
dev_err(&client->dev, "regulator init failed (%d)\n", ret);
@ -241,21 +240,19 @@ static int max8952_pmic_probe(struct i2c_client *client,
if (gpio_is_valid(pdata->gpio_vid0) &&
gpio_is_valid(pdata->gpio_vid1)) {
if (!gpio_request(pdata->gpio_vid0, "MAX8952 VID0"))
gpio_direction_output(pdata->gpio_vid0,
(pdata->default_mode) & 0x1);
else
unsigned long gpio_flags;
gpio_flags = max8952->vid0 ?
GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
if (devm_gpio_request_one(&client->dev, pdata->gpio_vid0,
gpio_flags, "MAX8952 VID0"))
err = 1;
if (!gpio_request(pdata->gpio_vid1, "MAX8952 VID1"))
gpio_direction_output(pdata->gpio_vid1,
(pdata->default_mode >> 1) & 0x1);
else {
if (!err)
gpio_free(pdata->gpio_vid0);
gpio_flags = max8952->vid1 ?
GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
if (devm_gpio_request_one(&client->dev, pdata->gpio_vid1,
gpio_flags, "MAX8952 VID1"))
err = 2;
}
} else
err = 3;
@ -314,16 +311,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
return 0;
}
static int max8952_pmic_remove(struct i2c_client *client)
{
struct max8952_data *max8952 = i2c_get_clientdata(client);
struct max8952_platform_data *pdata = max8952->pdata;
gpio_free(pdata->gpio_vid0);
gpio_free(pdata->gpio_vid1);
return 0;
}
static const struct i2c_device_id max8952_ids[] = {
{ "max8952", 0 },
{ },
@ -332,7 +319,6 @@ MODULE_DEVICE_TABLE(i2c, max8952_ids);
static struct i2c_driver max8952_pmic_driver = {
.probe = max8952_pmic_probe,
.remove = max8952_pmic_remove,
.driver = {
.name = "max8952",
.of_match_table = of_match_ptr(max8952_dt_match),

37
drivers/regulator/mc13xxx-regulator-core.c
View File

@ -33,17 +33,12 @@ static int mc13xxx_regulator_enable(struct regulator_dev *rdev)
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit,
mc13xxx_regulators[id].enable_bit);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit,
mc13xxx_regulators[id].enable_bit);
}
static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
@ -51,16 +46,11 @@ static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit, 0);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit, 0);
}
static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
@ -70,10 +60,7 @@ static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
int ret, id = rdev_get_id(rdev);
unsigned int val;
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
mc13xxx_unlock(priv->mc13xxx);
if (ret)
return ret;
@ -86,15 +73,10 @@ static int mc13xxx_regulator_set_voltage_sel(struct regulator_dev *rdev,
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg,
mc13xxx_regulators[id].vsel_mask,
selector << mc13xxx_regulators[id].vsel_shift);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg,
mc13xxx_regulators[id].vsel_mask,
selector << mc13xxx_regulators[id].vsel_shift);
}
static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
@ -106,11 +88,8 @@ static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_read(priv->mc13xxx,
mc13xxx_regulators[id].vsel_reg, &val);
mc13xxx_unlock(priv->mc13xxx);
if (ret)
return ret;

1
drivers/regulator/mc13xxx.h
View File

@ -21,7 +21,6 @@ struct mc13xxx_regulator {
int vsel_reg;
int vsel_shift;
int vsel_mask;
int hi_bit;
};
struct mc13xxx_regulator_priv {

1164
drivers/regulator/palmas-regulator.c
View File

File diff suppressed because it is too large Load Diff

837
include/linux/mfd/palmas.h
View File

@ -30,6 +30,8 @@
#define PALMAS_CHIP_ID 0xC035
#define PALMAS_CHIP_CHARGER_ID 0xC036
#define TPS65917_RESERVED -1
#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
((a) == PALMAS_CHIP_ID))
#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
@ -51,6 +53,8 @@ struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
struct palmas_usb;
struct palmas_pmic_driver_data;
struct palmas_pmic_platform_data;
enum palmas_usb_state {
PALMAS_USB_STATE_DISCONNECT,
@ -74,6 +78,8 @@ struct palmas {
struct mutex irq_lock;
struct regmap_irq_chip_data *irq_data;
struct palmas_pmic_driver_data *pmic_ddata;
/* Child Devices */
struct palmas_pmic *pmic;
struct palmas_gpadc *gpadc;
@ -86,6 +92,46 @@ struct palmas {
u8 pwm_muxed;
};
#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
PALMAS_EXT_CONTROL_ENABLE2 | \
PALMAS_EXT_CONTROL_NSLEEP)
struct palmas_sleep_requestor_info {
int id;
int reg_offset;
int bit_pos;
};
struct palmas_regs_info {
char *name;
char *sname;
u8 vsel_addr;
u8 ctrl_addr;
u8 tstep_addr;
int sleep_id;
};
struct palmas_pmic_driver_data {
int smps_start;
int smps_end;
int ldo_begin;
int ldo_end;
int max_reg;
struct palmas_regs_info *palmas_regs_info;
struct of_regulator_match *palmas_matches;
struct palmas_sleep_requestor_info *sleep_req_info;
int (*smps_register)(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config);
int (*ldo_register)(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config);
};
struct palmas_gpadc_platform_data {
/* Channel 3 current source is only enabled during conversion */
int ch3_current;
@ -184,6 +230,27 @@ enum palmas_regulators {
PALMAS_NUM_REGS,
};
enum tps65917_regulators {
/* SMPS regulators */
TPS65917_REG_SMPS1,
TPS65917_REG_SMPS2,
TPS65917_REG_SMPS3,
TPS65917_REG_SMPS4,
TPS65917_REG_SMPS5,
/* LDO regulators */
TPS65917_REG_LDO1,
TPS65917_REG_LDO2,
TPS65917_REG_LDO3,
TPS65917_REG_LDO4,
TPS65917_REG_LDO5,
TPS65917_REG_REGEN1,
TPS65917_REG_REGEN2,
TPS65917_REG_REGEN3,
/* Total number of regulators */
TPS65917_NUM_REGS,
};
/* External controll signal name */
enum {
PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
@ -228,6 +295,24 @@ enum palmas_external_requestor_id {
PALMAS_EXTERNAL_REQSTR_ID_MAX,
};
enum tps65917_external_requestor_id {
TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
TPS65917_EXTERNAL_REQSTR_ID_LDO1,
TPS65917_EXTERNAL_REQSTR_ID_LDO2,
TPS65917_EXTERNAL_REQSTR_ID_LDO3,
TPS65917_EXTERNAL_REQSTR_ID_LDO4,
TPS65917_EXTERNAL_REQSTR_ID_LDO5,
/* Last entry */
TPS65917_EXTERNAL_REQSTR_ID_MAX,
};
struct palmas_pmic_platform_data {
/* An array of pointers to regulator init data indexed by regulator
* ID
@ -349,6 +434,48 @@ struct palmas_gpadc_result {
#define PALMAS_MAX_CHANNELS 16
/* Define the tps65917 IRQ numbers */
enum tps65917_irqs {
/* INT1 registers */
TPS65917_RESERVED1,
TPS65917_PWRON_IRQ,
TPS65917_LONG_PRESS_KEY_IRQ,
TPS65917_RESERVED2,
TPS65917_PWRDOWN_IRQ,
TPS65917_HOTDIE_IRQ,
TPS65917_VSYS_MON_IRQ,
TPS65917_RESERVED3,
/* INT2 registers */
TPS65917_RESERVED4,
TPS65917_OTP_ERROR_IRQ,
TPS65917_WDT_IRQ,
TPS65917_RESERVED5,
TPS65917_RESET_IN_IRQ,
TPS65917_FSD_IRQ,
TPS65917_SHORT_IRQ,
TPS65917_RESERVED6,
/* INT3 registers */
TPS65917_GPADC_AUTO_0_IRQ,
TPS65917_GPADC_AUTO_1_IRQ,
TPS65917_GPADC_EOC_SW_IRQ,
TPS65917_RESREVED6,
TPS65917_RESERVED7,
TPS65917_RESERVED8,
TPS65917_RESERVED9,
TPS65917_VBUS_IRQ,
/* INT4 registers */
TPS65917_GPIO_0_IRQ,
TPS65917_GPIO_1_IRQ,
TPS65917_GPIO_2_IRQ,
TPS65917_GPIO_3_IRQ,
TPS65917_GPIO_4_IRQ,
TPS65917_GPIO_5_IRQ,
TPS65917_GPIO_6_IRQ,
TPS65917_RESERVED10,
/* Total Number IRQs */
TPS65917_NUM_IRQ,
};
/* Define the palmas IRQ numbers */
enum palmas_irqs {
/* INT1 registers */
@ -400,6 +527,7 @@ struct palmas_pmic {
int smps123;
int smps457;
int smps12;
int range[PALMAS_REG_SMPS10_OUT1];
unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
@ -2871,6 +2999,715 @@ enum usb_irq_events {
#define PALMAS_GPADC_TRIM15 0x0E
#define PALMAS_GPADC_TRIM16 0x0F
/* TPS65917 Interrupt registers */
/* Registers for function INTERRUPT */
#define TPS65917_INT1_STATUS 0x00
#define TPS65917_INT1_MASK 0x01
#define TPS65917_INT1_LINE_STATE 0x02
#define TPS65917_INT2_STATUS 0x05
#define TPS65917_INT2_MASK 0x06
#define TPS65917_INT2_LINE_STATE 0x07
#define TPS65917_INT3_STATUS 0x0A
#define TPS65917_INT3_MASK 0x0B
#define TPS65917_INT3_LINE_STATE 0x0C
#define TPS65917_INT4_STATUS 0x0F
#define TPS65917_INT4_MASK 0x10
#define TPS65917_INT4_LINE_STATE 0x11
#define TPS65917_INT4_EDGE_DETECT1 0x12
#define TPS65917_INT4_EDGE_DETECT2 0x13
#define TPS65917_INT_CTRL 0x14
/* Bit definitions for INT1_STATUS */
#define TPS65917_INT1_STATUS_VSYS_MON 0x40
#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_STATUS_HOTDIE 0x20
#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_STATUS_PWRDOWN 0x10
#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_STATUS_PWRON 0x02
#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
/* Bit definitions for INT1_MASK */
#define TPS65917_INT1_MASK_VSYS_MON 0x40
#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_MASK_HOTDIE 0x20
#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_MASK_PWRDOWN 0x10
#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_MASK_PWRON 0x02
#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
/* Bit definitions for INT1_LINE_STATE */
#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_LINE_STATE_PWRON 0x02
#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
/* Bit definitions for INT2_STATUS */
#define TPS65917_INT2_STATUS_SHORT 0x40
#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
#define TPS65917_INT2_STATUS_FSD 0x20
#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
#define TPS65917_INT2_STATUS_RESET_IN 0x10
#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_STATUS_WDT 0x04
#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT2_MASK */
#define TPS65917_INT2_MASK_SHORT 0x40
#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
#define TPS65917_INT2_MASK_FSD 0x20
#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
#define TPS65917_INT2_MASK_RESET_IN 0x10
#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_MASK_WDT 0x04
#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT2_LINE_STATE */
#define TPS65917_INT2_LINE_STATE_SHORT 0x40
#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
#define TPS65917_INT2_LINE_STATE_FSD 0x20
#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_LINE_STATE_WDT 0x04
#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT3_STATUS */
#define TPS65917_INT3_STATUS_VBUS 0x80
#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT3_MASK */
#define TPS65917_INT3_MASK_VBUS 0x80
#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT3_LINE_STATE */
#define TPS65917_INT3_LINE_STATE_VBUS 0x80
#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT4_STATUS */
#define TPS65917_INT4_STATUS_GPIO_6 0x40
#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_STATUS_GPIO_5 0x20
#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_STATUS_GPIO_4 0x10
#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_STATUS_GPIO_3 0x08
#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_STATUS_GPIO_2 0x04
#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_STATUS_GPIO_1 0x02
#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_STATUS_GPIO_0 0x01
#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_MASK */
#define TPS65917_INT4_MASK_GPIO_6 0x40
#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_MASK_GPIO_5 0x20
#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_MASK_GPIO_4 0x10
#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_MASK_GPIO_3 0x08
#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_MASK_GPIO_2 0x04
#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_MASK_GPIO_1 0x02
#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_MASK_GPIO_0 0x01
#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_LINE_STATE */
#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_EDGE_DETECT1 */
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
/* Bit definitions for INT4_EDGE_DETECT2 */
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
/* Bit definitions for INT_CTRL */
#define TPS65917_INT_CTRL_INT_PENDING 0x04
#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
#define TPS65917_INT_CTRL_INT_CLEAR 0x01
#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
/* TPS65917 SMPS Registers */
/* Registers for function SMPS */
#define TPS65917_SMPS1_CTRL 0x00
#define TPS65917_SMPS1_FORCE 0x02
#define TPS65917_SMPS1_VOLTAGE 0x03
#define TPS65917_SMPS2_CTRL 0x04
#define TPS65917_SMPS2_FORCE 0x06
#define TPS65917_SMPS2_VOLTAGE 0x07
#define TPS65917_SMPS3_CTRL 0x0C
#define TPS65917_SMPS3_FORCE 0x0E
#define TPS65917_SMPS3_VOLTAGE 0x0F
#define TPS65917_SMPS4_CTRL 0x10
#define TPS65917_SMPS4_VOLTAGE 0x13
#define TPS65917_SMPS5_CTRL 0x18
#define TPS65917_SMPS5_VOLTAGE 0x1B
#define TPS65917_SMPS_CTRL 0x24
#define TPS65917_SMPS_PD_CTRL 0x25
#define TPS65917_SMPS_THERMAL_EN 0x27
#define TPS65917_SMPS_THERMAL_STATUS 0x28
#define TPS65917_SMPS_SHORT_STATUS 0x29
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
/* Bit definitions for SMPS1_CTRL */
#define TPS65917_SMPS1_CTRL_WR_S 0x80
#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS1_FORCE */
#define TPS65917_SMPS1_FORCE_CMD 0x80
#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS1_VOLTAGE */
#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS2_CTRL */
#define TPS65917_SMPS2_CTRL_WR_S 0x80
#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS2_FORCE */
#define TPS65917_SMPS2_FORCE_CMD 0x80
#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS2_VOLTAGE */
#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS3_CTRL */
#define TPS65917_SMPS3_CTRL_WR_S 0x80
#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS3_FORCE */
#define TPS65917_SMPS3_FORCE_CMD 0x80
#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS3_VOLTAGE */
#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS4_CTRL */
#define TPS65917_SMPS4_CTRL_WR_S 0x80
#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS4_VOLTAGE */
#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS5_CTRL */
#define TPS65917_SMPS5_CTRL_WR_S 0x80
#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS5_VOLTAGE */
#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS_CTRL */
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
/* Bit definitions for SMPS_PD_CTRL */
#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_THERMAL_EN */
#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
/* Bit definitions for SMPS_THERMAL_STATUS */
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
/* Bit definitions for SMPS_SHORT_STATUS */
#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_POWERGOOD_MASK1 */
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_POWERGOOD_MASK2 */
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
/* Bit definitions for SMPS_PLL_CTRL */
#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
/* Registers for function LDO */
#define TPS65917_LDO1_CTRL 0x00
#define TPS65917_LDO1_VOLTAGE 0x01
#define TPS65917_LDO2_CTRL 0x02
#define TPS65917_LDO2_VOLTAGE 0x03
#define TPS65917_LDO3_CTRL 0x04
#define TPS65917_LDO3_VOLTAGE 0x05
#define TPS65917_LDO4_CTRL 0x0E
#define TPS65917_LDO4_VOLTAGE 0x0F
#define TPS65917_LDO5_CTRL 0x12
#define TPS65917_LDO5_VOLTAGE 0x13
#define TPS65917_LDO_PD_CTRL1 0x1B
#define TPS65917_LDO_PD_CTRL2 0x1C
#define TPS65917_LDO_SHORT_STATUS1 0x1D
#define TPS65917_LDO_SHORT_STATUS2 0x1E
#define TPS65917_LDO_PD_CTRL3 0x2D
#define TPS65917_LDO_SHORT_STATUS3 0x2E
/* Bit definitions for LDO1_CTRL */
#define TPS65917_LDO1_CTRL_WR_S 0x80
#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
#define TPS65917_LDO1_CTRL_STATUS 0x10
#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO1_VOLTAGE */
#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO2_CTRL */
#define TPS65917_LDO2_CTRL_WR_S 0x80
#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
#define TPS65917_LDO2_CTRL_STATUS 0x10
#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO2_VOLTAGE */
#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO3_CTRL */
#define TPS65917_LDO3_CTRL_WR_S 0x80
#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO3_CTRL_STATUS 0x10
#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO3_VOLTAGE */
#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO4_CTRL */
#define TPS65917_LDO4_CTRL_WR_S 0x80
#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO4_CTRL_STATUS 0x10
#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO4_VOLTAGE */
#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO5_CTRL */
#define TPS65917_LDO5_CTRL_WR_S 0x80
#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO5_CTRL_STATUS 0x10
#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO5_VOLTAGE */
#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO_PD_CTRL1 */
#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
/* Bit definitions for LDO_PD_CTRL2 */
#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
/* Bit definitions for LDO_PD_CTRL3 */
#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
/* Bit definitions for LDO_SHORT_STATUS1 */
#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
/* Bit definitions for REGEN1_CTRL */
#define TPS65917_REGEN1_CTRL_STATUS 0x10
#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for PLLEN_CTRL */
#define TPS65917_PLLEN_CTRL_STATUS 0x10
#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for REGEN2_CTRL */
#define TPS65917_REGEN2_CTRL_STATUS 0x10
#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for NSLEEP_RES_ASSIGN */
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for NSLEEP_SMPS_ASSIGN */
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for ENABLE1_RES_ASSIGN */
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for ENABLE1_SMPS_ASSIGN */
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for ENABLE2_RES_ASSIGN */
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for ENABLE2_SMPS_ASSIGN */
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for REGEN3_CTRL */
#define TPS65917_REGEN3_CTRL_STATUS 0x10
#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Registers for function RESOURCE */
#define TPS65917_REGEN1_CTRL 0x2
#define TPS65917_PLLEN_CTRL 0x3
#define TPS65917_NSLEEP_RES_ASSIGN 0x6
#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
#define TPS65917_ENABLE1_RES_ASSIGN 0xA
#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
#define TPS65917_ENABLE2_RES_ASSIGN 0xE
#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
#define TPS65917_REGEN2_CTRL 0x12
#define TPS65917_REGEN3_CTRL 0x13
static inline int palmas_read(struct palmas *palmas, unsigned int base,
unsigned int reg, unsigned int *val)
{