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drm/nv40-50/gr: restructure grctx/prog generation
The conditional definition of the generation helper functions apparently confuses some IDEs.... Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a8f81837c5
commit
d58086deaa
@ -1286,13 +1286,15 @@ extern int nv20_graph_create(struct drm_device *);
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/* nv40_graph.c */
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extern int nv40_graph_create(struct drm_device *);
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extern void nv40_grctx_init(struct nouveau_grctx *);
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extern void nv40_grctx_init(struct drm_device *, u32 *size);
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extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
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/* nv50_graph.c */
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extern int nv50_graph_create(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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extern struct nouveau_enum nv50_data_error_names[];
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extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
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extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
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extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
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/* nvc0_graph.c */
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extern int nvc0_graph_create(struct drm_device *);
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@ -18,7 +18,6 @@ struct nouveau_grctx {
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uint32_t ctxvals_base;
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};
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#ifdef CP_CTX
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static inline void
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cp_out(struct nouveau_grctx *ctx, uint32_t inst)
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{
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@ -88,10 +87,8 @@ _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
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(state ? 0 : CP_BRA_IF_CLEAR));
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}
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#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
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#ifdef CP_BRA_MOD
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#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
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#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
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#endif
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static inline void
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_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
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@ -128,6 +125,5 @@ gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)
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nv_wo32(ctx->data, reg * 4, val);
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}
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#endif
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#endif
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@ -27,7 +27,6 @@
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_grctx.h"
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#include "nouveau_ramht.h"
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struct nv40_graph_engine {
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@ -42,7 +41,6 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine)
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *grctx = NULL;
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struct nouveau_grctx ctx = {};
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unsigned long flags;
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int ret;
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@ -52,11 +50,7 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine)
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return ret;
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/* Initialise default context values */
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = grctx;
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nv40_grctx_init(&ctx);
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nv40_grctx_fill(dev, grctx);
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nv_wo32(grctx, 0, grctx->vinst);
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/* init grctx pointer in ramfc, and on PFIFO if channel is
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@ -184,8 +178,7 @@ nv40_graph_init(struct drm_device *dev, int engine)
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struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct nouveau_grctx ctx = {};
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uint32_t vramsz, *cp;
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uint32_t vramsz;
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int i, j;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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@ -193,22 +186,8 @@ nv40_graph_init(struct drm_device *dev, int engine)
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 256;
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nv40_grctx_init(&ctx);
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pgraph->grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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kfree(cp);
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/* generate and upload context program */
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nv40_grctx_init(dev, &pgraph->grctx_size);
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/* No context present currently */
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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@ -595,8 +595,8 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx)
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}
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}
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void
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nv40_grctx_init(struct nouveau_grctx *ctx)
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static void
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nv40_grctx_generate(struct nouveau_grctx *ctx)
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{
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/* decide whether we're loading/unloading the context */
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cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
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@ -660,3 +660,31 @@ nv40_grctx_init(struct nouveau_grctx *ctx)
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cp_out (ctx, CP_END);
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}
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void
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nv40_grctx_fill(struct drm_device *dev, struct nouveau_gpuobj *mem)
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{
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nv40_grctx_generate(&(struct nouveau_grctx) {
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.dev = dev,
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.mode = NOUVEAU_GRCTX_VALS,
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.data = mem,
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});
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}
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void
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nv40_grctx_init(struct drm_device *dev, u32 *size)
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{
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u32 ctxprog[256], i;
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struct nouveau_grctx ctx = {
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.dev = dev,
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.mode = NOUVEAU_GRCTX_PROG,
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.data = ctxprog,
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.ctxprog_max = ARRAY_SIZE(ctxprog)
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};
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nv40_grctx_generate(&ctx);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, ctxprog[i]);
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*size = ctx.ctxvals_pos * 4;
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}
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@ -28,7 +28,6 @@
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#include "nouveau_grctx.h"
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#include "nouveau_dma.h"
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#include "nouveau_vm.h"
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#include "nv50_evo.h"
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@ -229,7 +228,6 @@ nv50_graph_context_new(struct nouveau_channel *chan, int engine)
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_gpuobj *grctx = NULL;
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struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
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struct nouveau_grctx ctx = {};
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int hdr, ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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@ -248,11 +246,7 @@ nv50_graph_context_new(struct nouveau_channel *chan, int engine)
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nv_wo32(ramin, hdr + 0x10, 0);
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nv_wo32(ramin, hdr + 0x14, 0x00010000);
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = grctx;
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nv50_grctx_init(&ctx);
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nv50_grctx_fill(dev, grctx);
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nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
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dev_priv->engine.instmem.flush(dev);
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@ -996,28 +990,21 @@ nv50_graph_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_graph_engine *pgraph;
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struct nouveau_grctx ctx = {};
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int ret;
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pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
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if (!pgraph)
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return -ENOMEM;
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = pgraph->ctxprog;
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ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);
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ret = nv50_grctx_init(&ctx);
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ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog),
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&pgraph->ctxprog_size,
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&pgraph->grctx_size);
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if (ret) {
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NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
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kfree(pgraph);
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return 0;
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}
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pgraph->grctx_size = ctx.ctxvals_pos * 4;
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pgraph->ctxprog_size = ctx.ctxprog_len;
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pgraph->base.destroy = nv50_graph_destroy;
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pgraph->base.init = nv50_graph_init;
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pgraph->base.fini = nv50_graph_fini;
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@ -172,8 +172,8 @@ static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
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/* Main function: construct the ctxprog skeleton, call the other functions. */
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int
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nv50_grctx_init(struct nouveau_grctx *ctx)
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static int
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nv50_grctx_generate(struct nouveau_grctx *ctx)
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{
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struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
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@ -277,6 +277,33 @@ nv50_grctx_init(struct nouveau_grctx *ctx)
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return 0;
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}
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void
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nv50_grctx_fill(struct drm_device *dev, struct nouveau_gpuobj *mem)
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{
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nv50_grctx_generate(&(struct nouveau_grctx) {
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.dev = dev,
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.mode = NOUVEAU_GRCTX_VALS,
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.data = mem,
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});
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}
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int
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nv50_grctx_init(struct drm_device *dev, u32 *data, u32 max, u32 *len, u32 *cnt)
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{
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struct nouveau_grctx ctx = {
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.dev = dev,
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.mode = NOUVEAU_GRCTX_PROG,
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.data = data,
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.ctxprog_max = max
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};
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int ret;
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ret = nv50_grctx_generate(&ctx);
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*cnt = ctx.ctxvals_pos * 4;
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*len = ctx.ctxprog_len;
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return ret;
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}
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/*
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* Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
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* registers to save/restore and the default values for them.
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