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drm/amdgpu: reorder CS code
Sort the functions in the order they are called Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
88c98d54b2
commit
d4e8ad908b
@ -278,6 +278,323 @@ free_chunk:
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return ret;
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}
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static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
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struct amdgpu_cs_parser *parser)
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{
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struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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int r, ce_preempt = 0, de_preempt = 0;
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struct amdgpu_ring *ring;
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int i, j;
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for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
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struct amdgpu_cs_chunk *chunk;
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struct amdgpu_ib *ib;
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struct drm_amdgpu_cs_chunk_ib *chunk_ib;
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struct drm_sched_entity *entity;
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chunk = &parser->chunks[i];
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ib = &parser->job->ibs[j];
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chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
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if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
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continue;
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if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
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chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
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if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
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ce_preempt++;
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else
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de_preempt++;
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/* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
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if (ce_preempt > 1 || de_preempt > 1)
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return -EINVAL;
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}
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r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
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chunk_ib->ip_instance, chunk_ib->ring,
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&entity);
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if (r)
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return r;
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if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
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parser->job->preamble_status |=
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AMDGPU_PREAMBLE_IB_PRESENT;
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if (parser->entity && parser->entity != entity)
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return -EINVAL;
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/* Return if there is no run queue associated with this entity.
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* Possibly because of disabled HW IP*/
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if (entity->rq == NULL)
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return -EINVAL;
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parser->entity = entity;
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ring = to_amdgpu_ring(entity->rq->sched);
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r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
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chunk_ib->ib_bytes : 0,
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AMDGPU_IB_POOL_DELAYED, ib);
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if (r) {
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DRM_ERROR("Failed to get ib !\n");
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return r;
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}
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ib->gpu_addr = chunk_ib->va_start;
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ib->length_dw = chunk_ib->ib_bytes / 4;
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ib->flags = chunk_ib->flags;
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j++;
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}
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/* MM engine doesn't support user fences */
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ring = to_amdgpu_ring(parser->entity->rq->sched);
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if (parser->job->uf_addr && ring->funcs->no_user_fence)
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return -EINVAL;
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return 0;
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}
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static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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{
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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unsigned num_deps;
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int i, r;
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struct drm_amdgpu_cs_chunk_dep *deps;
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deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_dep);
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for (i = 0; i < num_deps; ++i) {
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struct amdgpu_ctx *ctx;
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struct drm_sched_entity *entity;
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struct dma_fence *fence;
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ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
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if (ctx == NULL)
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return -EINVAL;
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r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
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deps[i].ip_instance,
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deps[i].ring, &entity);
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if (r) {
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amdgpu_ctx_put(ctx);
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return r;
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}
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fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
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amdgpu_ctx_put(ctx);
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if (IS_ERR(fence))
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return PTR_ERR(fence);
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else if (!fence)
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continue;
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if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
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struct drm_sched_fence *s_fence;
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struct dma_fence *old = fence;
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s_fence = to_drm_sched_fence(fence);
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fence = dma_fence_get(&s_fence->scheduled);
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dma_fence_put(old);
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}
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r = amdgpu_sync_fence(&p->job->sync, fence);
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dma_fence_put(fence);
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if (r)
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return r;
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}
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return 0;
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}
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static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
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uint32_t handle, u64 point,
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u64 flags)
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{
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struct dma_fence *fence;
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int r;
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r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
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if (r) {
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DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
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handle, point, r);
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return r;
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}
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r = amdgpu_sync_fence(&p->job->sync, fence);
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dma_fence_put(fence);
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return r;
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}
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static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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{
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struct drm_amdgpu_cs_chunk_sem *deps;
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unsigned num_deps;
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int i, r;
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deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_sem);
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for (i = 0; i < num_deps; ++i) {
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r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
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0, 0);
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if (r)
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return r;
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}
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return 0;
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}
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static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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{
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struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
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unsigned num_deps;
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int i, r;
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syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_syncobj);
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for (i = 0; i < num_deps; ++i) {
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r = amdgpu_syncobj_lookup_and_add_to_sync(p,
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syncobj_deps[i].handle,
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syncobj_deps[i].point,
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syncobj_deps[i].flags);
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if (r)
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return r;
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}
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return 0;
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}
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static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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{
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struct drm_amdgpu_cs_chunk_sem *deps;
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unsigned num_deps;
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int i;
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deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_sem);
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if (p->post_deps)
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return -EINVAL;
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p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
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GFP_KERNEL);
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p->num_post_deps = 0;
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if (!p->post_deps)
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return -ENOMEM;
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for (i = 0; i < num_deps; ++i) {
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p->post_deps[i].syncobj =
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drm_syncobj_find(p->filp, deps[i].handle);
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if (!p->post_deps[i].syncobj)
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return -EINVAL;
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p->post_deps[i].chain = NULL;
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p->post_deps[i].point = 0;
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p->num_post_deps++;
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}
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return 0;
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}
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static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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{
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struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
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unsigned num_deps;
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int i;
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syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_syncobj);
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if (p->post_deps)
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return -EINVAL;
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p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
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GFP_KERNEL);
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p->num_post_deps = 0;
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if (!p->post_deps)
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return -ENOMEM;
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for (i = 0; i < num_deps; ++i) {
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struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
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dep->chain = NULL;
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if (syncobj_deps[i].point) {
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dep->chain = dma_fence_chain_alloc();
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if (!dep->chain)
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return -ENOMEM;
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}
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dep->syncobj = drm_syncobj_find(p->filp,
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syncobj_deps[i].handle);
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if (!dep->syncobj) {
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dma_fence_chain_free(dep->chain);
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return -EINVAL;
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}
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dep->point = syncobj_deps[i].point;
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p->num_post_deps++;
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}
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return 0;
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}
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static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
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struct amdgpu_cs_parser *p)
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{
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int i, r;
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for (i = 0; i < p->nchunks; ++i) {
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struct amdgpu_cs_chunk *chunk;
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chunk = &p->chunks[i];
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switch (chunk->chunk_id) {
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case AMDGPU_CHUNK_ID_DEPENDENCIES:
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case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
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r = amdgpu_cs_process_fence_dep(p, chunk);
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if (r)
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return r;
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break;
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case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
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r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
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if (r)
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return r;
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break;
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case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
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r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
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if (r)
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return r;
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break;
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case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
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r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
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if (r)
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return r;
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break;
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case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
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r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
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if (r)
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return r;
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break;
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}
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}
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return 0;
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}
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/* Convert microseconds to bytes. */
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static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
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{
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@ -659,25 +976,15 @@ out_free_user_pages:
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return r;
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}
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static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
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static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
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{
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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struct amdgpu_bo_list_entry *e;
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int r;
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int i;
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list_for_each_entry(e, &p->validated, tv.head) {
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struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
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struct dma_resv *resv = bo->tbo.base.resv;
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enum amdgpu_sync_mode sync_mode;
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if (!trace_amdgpu_cs_enabled())
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return;
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sync_mode = amdgpu_bo_explicit_sync(bo) ?
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AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
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r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
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&fpriv->vm);
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if (r)
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return r;
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}
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return 0;
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for (i = 0; i < parser->job->num_ibs; i++)
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trace_amdgpu_cs(parser, i);
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}
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static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
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@ -753,8 +1060,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
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}
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if (!p->job->vm)
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return amdgpu_cs_sync_rings(p);
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return 0;
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r = amdgpu_vm_clear_freed(adev, vm, NULL);
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if (r)
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@ -826,324 +1132,27 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
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}
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}
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return amdgpu_cs_sync_rings(p);
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}
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static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
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struct amdgpu_cs_parser *parser)
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{
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struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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int r, ce_preempt = 0, de_preempt = 0;
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struct amdgpu_ring *ring;
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int i, j;
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for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
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struct amdgpu_cs_chunk *chunk;
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struct amdgpu_ib *ib;
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struct drm_amdgpu_cs_chunk_ib *chunk_ib;
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struct drm_sched_entity *entity;
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chunk = &parser->chunks[i];
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ib = &parser->job->ibs[j];
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chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
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if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
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continue;
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if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
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chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
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if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
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ce_preempt++;
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else
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de_preempt++;
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/* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
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if (ce_preempt > 1 || de_preempt > 1)
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return -EINVAL;
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}
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r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
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chunk_ib->ip_instance, chunk_ib->ring,
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&entity);
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if (r)
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return r;
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if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
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parser->job->preamble_status |=
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AMDGPU_PREAMBLE_IB_PRESENT;
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if (parser->entity && parser->entity != entity)
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return -EINVAL;
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/* Return if there is no run queue associated with this entity.
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* Possibly because of disabled HW IP*/
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if (entity->rq == NULL)
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return -EINVAL;
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parser->entity = entity;
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ring = to_amdgpu_ring(entity->rq->sched);
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r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
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chunk_ib->ib_bytes : 0,
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AMDGPU_IB_POOL_DELAYED, ib);
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if (r) {
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DRM_ERROR("Failed to get ib !\n");
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return r;
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}
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ib->gpu_addr = chunk_ib->va_start;
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ib->length_dw = chunk_ib->ib_bytes / 4;
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ib->flags = chunk_ib->flags;
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j++;
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}
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/* MM engine doesn't support user fences */
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ring = to_amdgpu_ring(parser->entity->rq->sched);
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if (parser->job->uf_addr && ring->funcs->no_user_fence)
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return -EINVAL;
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return 0;
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}
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static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
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struct amdgpu_cs_chunk *chunk)
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static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
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{
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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unsigned num_deps;
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int i, r;
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struct drm_amdgpu_cs_chunk_dep *deps;
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|
||||
deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
|
||||
num_deps = chunk->length_dw * 4 /
|
||||
sizeof(struct drm_amdgpu_cs_chunk_dep);
|
||||
|
||||
for (i = 0; i < num_deps; ++i) {
|
||||
struct amdgpu_ctx *ctx;
|
||||
struct drm_sched_entity *entity;
|
||||
struct dma_fence *fence;
|
||||
|
||||
ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
|
||||
if (ctx == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
|
||||
deps[i].ip_instance,
|
||||
deps[i].ring, &entity);
|
||||
if (r) {
|
||||
amdgpu_ctx_put(ctx);
|
||||
return r;
|
||||
}
|
||||
|
||||
fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
|
||||
amdgpu_ctx_put(ctx);
|
||||
|
||||
if (IS_ERR(fence))
|
||||
return PTR_ERR(fence);
|
||||
else if (!fence)
|
||||
continue;
|
||||
|
||||
if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
|
||||
struct drm_sched_fence *s_fence;
|
||||
struct dma_fence *old = fence;
|
||||
|
||||
s_fence = to_drm_sched_fence(fence);
|
||||
fence = dma_fence_get(&s_fence->scheduled);
|
||||
dma_fence_put(old);
|
||||
}
|
||||
|
||||
r = amdgpu_sync_fence(&p->job->sync, fence);
|
||||
dma_fence_put(fence);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
|
||||
uint32_t handle, u64 point,
|
||||
u64 flags)
|
||||
{
|
||||
struct dma_fence *fence;
|
||||
struct amdgpu_bo_list_entry *e;
|
||||
int r;
|
||||
|
||||
r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
|
||||
if (r) {
|
||||
DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
|
||||
handle, point, r);
|
||||
return r;
|
||||
}
|
||||
list_for_each_entry(e, &p->validated, tv.head) {
|
||||
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
|
||||
struct dma_resv *resv = bo->tbo.base.resv;
|
||||
enum amdgpu_sync_mode sync_mode;
|
||||
|
||||
r = amdgpu_sync_fence(&p->job->sync, fence);
|
||||
dma_fence_put(fence);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
|
||||
struct amdgpu_cs_chunk *chunk)
|
||||
{
|
||||
struct drm_amdgpu_cs_chunk_sem *deps;
|
||||
unsigned num_deps;
|
||||
int i, r;
|
||||
|
||||
deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
|
||||
num_deps = chunk->length_dw * 4 /
|
||||
sizeof(struct drm_amdgpu_cs_chunk_sem);
|
||||
for (i = 0; i < num_deps; ++i) {
|
||||
r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
|
||||
0, 0);
|
||||
sync_mode = amdgpu_bo_explicit_sync(bo) ?
|
||||
AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
|
||||
r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
|
||||
&fpriv->vm);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
|
||||
struct amdgpu_cs_chunk *chunk)
|
||||
{
|
||||
struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
|
||||
unsigned num_deps;
|
||||
int i, r;
|
||||
|
||||
syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
|
||||
num_deps = chunk->length_dw * 4 /
|
||||
sizeof(struct drm_amdgpu_cs_chunk_syncobj);
|
||||
for (i = 0; i < num_deps; ++i) {
|
||||
r = amdgpu_syncobj_lookup_and_add_to_sync(p,
|
||||
syncobj_deps[i].handle,
|
||||
syncobj_deps[i].point,
|
||||
syncobj_deps[i].flags);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
|
||||
struct amdgpu_cs_chunk *chunk)
|
||||
{
|
||||
struct drm_amdgpu_cs_chunk_sem *deps;
|
||||
unsigned num_deps;
|
||||
int i;
|
||||
|
||||
deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
|
||||
num_deps = chunk->length_dw * 4 /
|
||||
sizeof(struct drm_amdgpu_cs_chunk_sem);
|
||||
|
||||
if (p->post_deps)
|
||||
return -EINVAL;
|
||||
|
||||
p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
|
||||
GFP_KERNEL);
|
||||
p->num_post_deps = 0;
|
||||
|
||||
if (!p->post_deps)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
for (i = 0; i < num_deps; ++i) {
|
||||
p->post_deps[i].syncobj =
|
||||
drm_syncobj_find(p->filp, deps[i].handle);
|
||||
if (!p->post_deps[i].syncobj)
|
||||
return -EINVAL;
|
||||
p->post_deps[i].chain = NULL;
|
||||
p->post_deps[i].point = 0;
|
||||
p->num_post_deps++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
|
||||
struct amdgpu_cs_chunk *chunk)
|
||||
{
|
||||
struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
|
||||
unsigned num_deps;
|
||||
int i;
|
||||
|
||||
syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
|
||||
num_deps = chunk->length_dw * 4 /
|
||||
sizeof(struct drm_amdgpu_cs_chunk_syncobj);
|
||||
|
||||
if (p->post_deps)
|
||||
return -EINVAL;
|
||||
|
||||
p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
|
||||
GFP_KERNEL);
|
||||
p->num_post_deps = 0;
|
||||
|
||||
if (!p->post_deps)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < num_deps; ++i) {
|
||||
struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
|
||||
|
||||
dep->chain = NULL;
|
||||
if (syncobj_deps[i].point) {
|
||||
dep->chain = dma_fence_chain_alloc();
|
||||
if (!dep->chain)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dep->syncobj = drm_syncobj_find(p->filp,
|
||||
syncobj_deps[i].handle);
|
||||
if (!dep->syncobj) {
|
||||
dma_fence_chain_free(dep->chain);
|
||||
return -EINVAL;
|
||||
}
|
||||
dep->point = syncobj_deps[i].point;
|
||||
p->num_post_deps++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
|
||||
struct amdgpu_cs_parser *p)
|
||||
{
|
||||
int i, r;
|
||||
|
||||
for (i = 0; i < p->nchunks; ++i) {
|
||||
struct amdgpu_cs_chunk *chunk;
|
||||
|
||||
chunk = &p->chunks[i];
|
||||
|
||||
switch (chunk->chunk_id) {
|
||||
case AMDGPU_CHUNK_ID_DEPENDENCIES:
|
||||
case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
|
||||
r = amdgpu_cs_process_fence_dep(p, chunk);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
|
||||
r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
|
||||
r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
|
||||
r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
|
||||
r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1243,17 +1252,6 @@ error_unlock:
|
||||
return r;
|
||||
}
|
||||
|
||||
static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!trace_amdgpu_cs_enabled())
|
||||
return;
|
||||
|
||||
for (i = 0; i < parser->job->num_ibs; i++)
|
||||
trace_amdgpu_cs(parser, i);
|
||||
}
|
||||
|
||||
/* Cleanup the parser structure */
|
||||
static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
|
||||
bool backoff)
|
||||
@ -1342,6 +1340,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
||||
if (r)
|
||||
goto out;
|
||||
|
||||
r = amdgpu_cs_sync_rings(&parser);
|
||||
if (r)
|
||||
goto out;
|
||||
|
||||
r = amdgpu_cs_submit(&parser, data);
|
||||
out:
|
||||
amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user