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ARM: sunxi: Add device tree for the A13 and the Olinuxino board

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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard 2012-11-14 20:17:04 +01:00
parent cb84fa18a4
commit d4da2ebb3e
3 changed files with 101 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
spear320-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

26
arch/arm/boot/dts/sun5i-olinuxino.dts Normal file
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@ -0,0 +1,26 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun5i.dtsi"
/ {
model = "Olimex A13-Olinuxino";
compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
soc {
duart: uart@01c28400 {
status = "okay";
};
};
};

74
arch/arm/boot/dts/sun5i.dtsi Normal file
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@ -0,0 +1,74 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&intc>;
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
memory {
reg = <0x40000000 0x20000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01c20000 0x300000>;
ranges;
timer@01c20c00 {
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sunxi-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: uart@01c28400 {
compatible = "ns8250";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
clock-frequency = <24000000>;
status = "disabled";
};
};
};