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powerpc/mpc83xx: Power Management support
Basic PM support for 83xx. Standby is implemented as sleep. Suspend-to-RAM is implemented as "deep sleep" (with the processor turned off) on 831x. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Scott Wood
Kumar Gala
parent
7e72063c9a
commit
d49747bdfb
@ -199,7 +199,7 @@ config ARCH_HIBERNATION_POSSIBLE
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config ARCH_SUSPEND_POSSIBLE
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def_bool y
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depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200
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depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx
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config PPC_DCR_NATIVE
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bool
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@ -3,6 +3,7 @@
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#
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obj-y := misc.o usb.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o
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obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
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obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
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obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
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533
arch/powerpc/platforms/83xx/suspend-asm.S
Normal file
533
arch/powerpc/platforms/83xx/suspend-asm.S
Normal file
@ -0,0 +1,533 @@
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/*
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* Enter and leave deep sleep state on MPC83xx
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*
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* Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
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#define SS_HID 0x08 /* 3 HIDs */
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#define SS_IABR 0x14 /* 2 IABRs */
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#define SS_IBCR 0x1c
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#define SS_DABR 0x20 /* 2 DABRs */
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#define SS_DBCR 0x28
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#define SS_SP 0x2c
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#define SS_SR 0x30 /* 16 segment registers */
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#define SS_R2 0x70
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#define SS_MSR 0x74
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#define SS_SDR1 0x78
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#define SS_LR 0x7c
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#define SS_SPRG 0x80 /* 4 SPRGs */
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#define SS_DBAT 0x90 /* 8 DBATs */
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#define SS_IBAT 0xd0 /* 8 IBATs */
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#define SS_TB 0x110
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#define SS_CR 0x118
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#define SS_GPREG 0x11c /* r12-r31 */
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#define STATE_SAVE_SIZE 0x16c
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.section .data
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.align 5
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mpc83xx_sleep_save_area:
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.space STATE_SAVE_SIZE
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immrbase:
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.long 0
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.section .text
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.align 5
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/* r3 = physical address of IMMR */
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_GLOBAL(mpc83xx_enter_deep_sleep)
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lis r4, immrbase@ha
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stw r3, immrbase@l(r4)
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/* The first 2 words of memory are used to communicate with the
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* bootloader, to tell it how to resume.
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*
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* The first word is the magic number 0xf5153ae5, and the second
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* is the pointer to mpc83xx_deep_resume.
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*
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* The original content of these two words is saved in SS_MEMSAVE.
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*/
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lis r3, mpc83xx_sleep_save_area@h
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ori r3, r3, mpc83xx_sleep_save_area@l
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lis r4, KERNELBASE@h
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lwz r5, 0(r4)
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lwz r6, 4(r4)
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stw r5, SS_MEMSAVE+0(r3)
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stw r6, SS_MEMSAVE+4(r3)
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mfspr r5, SPRN_HID0
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mfspr r6, SPRN_HID1
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mfspr r7, SPRN_HID2
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stw r5, SS_HID+0(r3)
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stw r6, SS_HID+4(r3)
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stw r7, SS_HID+8(r3)
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mfspr r4, SPRN_IABR
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mfspr r5, SPRN_IABR2
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mfspr r6, SPRN_IBCR
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mfspr r7, SPRN_DABR
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mfspr r8, SPRN_DABR2
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mfspr r9, SPRN_DBCR
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stw r4, SS_IABR+0(r3)
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stw r5, SS_IABR+4(r3)
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stw r6, SS_IBCR(r3)
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stw r7, SS_DABR+0(r3)
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stw r8, SS_DABR+4(r3)
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stw r9, SS_DBCR(r3)
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mfspr r4, SPRN_SPRG0
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mfspr r5, SPRN_SPRG1
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mfspr r6, SPRN_SPRG2
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mfspr r7, SPRN_SPRG3
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mfsdr1 r8
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stw r4, SS_SPRG+0(r3)
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stw r5, SS_SPRG+4(r3)
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stw r6, SS_SPRG+8(r3)
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stw r7, SS_SPRG+12(r3)
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stw r8, SS_SDR1(r3)
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mfspr r4, SPRN_DBAT0U
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mfspr r5, SPRN_DBAT0L
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mfspr r6, SPRN_DBAT1U
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mfspr r7, SPRN_DBAT1L
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stw r4, SS_DBAT+0x00(r3)
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stw r5, SS_DBAT+0x04(r3)
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stw r6, SS_DBAT+0x08(r3)
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stw r7, SS_DBAT+0x0c(r3)
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mfspr r4, SPRN_DBAT2U
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mfspr r5, SPRN_DBAT2L
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mfspr r6, SPRN_DBAT3U
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mfspr r7, SPRN_DBAT3L
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stw r4, SS_DBAT+0x10(r3)
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stw r5, SS_DBAT+0x14(r3)
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stw r6, SS_DBAT+0x18(r3)
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stw r7, SS_DBAT+0x1c(r3)
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mfspr r4, SPRN_DBAT4U
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mfspr r5, SPRN_DBAT4L
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mfspr r6, SPRN_DBAT5U
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mfspr r7, SPRN_DBAT5L
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stw r4, SS_DBAT+0x20(r3)
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stw r5, SS_DBAT+0x24(r3)
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stw r6, SS_DBAT+0x28(r3)
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stw r7, SS_DBAT+0x2c(r3)
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mfspr r4, SPRN_DBAT6U
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mfspr r5, SPRN_DBAT6L
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mfspr r6, SPRN_DBAT7U
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mfspr r7, SPRN_DBAT7L
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stw r4, SS_DBAT+0x30(r3)
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stw r5, SS_DBAT+0x34(r3)
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stw r6, SS_DBAT+0x38(r3)
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stw r7, SS_DBAT+0x3c(r3)
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mfspr r4, SPRN_IBAT0U
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mfspr r5, SPRN_IBAT0L
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mfspr r6, SPRN_IBAT1U
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mfspr r7, SPRN_IBAT1L
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stw r4, SS_IBAT+0x00(r3)
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stw r5, SS_IBAT+0x04(r3)
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stw r6, SS_IBAT+0x08(r3)
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stw r7, SS_IBAT+0x0c(r3)
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mfspr r4, SPRN_IBAT2U
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mfspr r5, SPRN_IBAT2L
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mfspr r6, SPRN_IBAT3U
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mfspr r7, SPRN_IBAT3L
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stw r4, SS_IBAT+0x10(r3)
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stw r5, SS_IBAT+0x14(r3)
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stw r6, SS_IBAT+0x18(r3)
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stw r7, SS_IBAT+0x1c(r3)
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mfspr r4, SPRN_IBAT4U
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mfspr r5, SPRN_IBAT4L
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mfspr r6, SPRN_IBAT5U
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mfspr r7, SPRN_IBAT5L
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stw r4, SS_IBAT+0x20(r3)
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stw r5, SS_IBAT+0x24(r3)
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stw r6, SS_IBAT+0x28(r3)
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stw r7, SS_IBAT+0x2c(r3)
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mfspr r4, SPRN_IBAT6U
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mfspr r5, SPRN_IBAT6L
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mfspr r6, SPRN_IBAT7U
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mfspr r7, SPRN_IBAT7L
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stw r4, SS_IBAT+0x30(r3)
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stw r5, SS_IBAT+0x34(r3)
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stw r6, SS_IBAT+0x38(r3)
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stw r7, SS_IBAT+0x3c(r3)
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mfmsr r4
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mflr r5
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mfcr r6
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stw r4, SS_MSR(r3)
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stw r5, SS_LR(r3)
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stw r6, SS_CR(r3)
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stw r1, SS_SP(r3)
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stw r2, SS_R2(r3)
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1: mftbu r4
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mftb r5
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mftbu r6
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cmpw r4, r6
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bne 1b
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stw r4, SS_TB+0(r3)
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stw r5, SS_TB+4(r3)
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stmw r12, SS_GPREG(r3)
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li r4, 0
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addi r6, r3, SS_SR-4
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1: mfsrin r5, r4
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stwu r5, 4(r6)
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addis r4, r4, 0x1000
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cmpwi r4, 0
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bne 1b
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/* Disable machine checks and critical exceptions */
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mfmsr r4
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rlwinm r4, r4, 0, ~MSR_CE
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rlwinm r4, r4, 0, ~MSR_ME
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mtmsr r4
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isync
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#define TMP_VIRT_IMMR 0xf0000000
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#define DEFAULT_IMMR_VALUE 0xff400000
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#define IMMRBAR_BASE 0x0000
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lis r4, immrbase@ha
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lwz r4, immrbase@l(r4)
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/* Use DBAT0 to address the current IMMR space */
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ori r4, r4, 0x002a
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mtspr SPRN_DBAT0L, r4
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lis r8, TMP_VIRT_IMMR@h
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ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
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mtspr SPRN_DBAT0U, r4
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isync
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/* Use DBAT1 to address the original IMMR space */
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lis r4, DEFAULT_IMMR_VALUE@h
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ori r4, r4, 0x002a
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mtspr SPRN_DBAT1L, r4
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lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
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ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
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mtspr SPRN_DBAT1U, r4
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isync
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/* Use DBAT2 to address the beginning of RAM. This isn't done
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* using the normal virtual mapping, because with page debugging
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* enabled it will be read-only.
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*/
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li r4, 0x0002
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mtspr SPRN_DBAT2L, r4
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lis r4, KERNELBASE@h
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ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
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mtspr SPRN_DBAT2U, r4
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isync
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/* Flush the cache with our BAT, as there will be TLB misses
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* otherwise if page debugging is enabled, and these misses
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* will disturb the PLRU algorithm.
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*/
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bl __flush_disable_L1
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/* Keep the i-cache enabled, so the hack below for low-boot
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* flash will work.
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*/
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mfspr r3, SPRN_HID0
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ori r3, r3, HID0_ICE
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mtspr SPRN_HID0, r3
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isync
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lis r6, 0xf515
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ori r6, r6, 0x3ae5
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lis r7, mpc83xx_deep_resume@h
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ori r7, r7, mpc83xx_deep_resume@l
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tophys(r7, r7)
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lis r5, KERNELBASE@h
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stw r6, 0(r5)
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stw r7, 4(r5)
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/* Reset BARs */
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li r4, 0
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stw r4, 0x0024(r8)
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stw r4, 0x002c(r8)
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stw r4, 0x0034(r8)
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stw r4, 0x003c(r8)
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stw r4, 0x0064(r8)
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stw r4, 0x006c(r8)
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/* Rev 1 of the 8313 has problems with wakeup events that are
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* pending during the transition to deep sleep state (such as if
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* the PCI host sets the state to D3 and then D0 in rapid
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* succession). This check shrinks the race window somewhat.
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*
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* See erratum PCI23, though the problem is not limited
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* to PCI.
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*/
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lwz r3, 0x0b04(r8)
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andi. r3, r3, 1
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bne- mpc83xx_deep_resume
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/* Move IMMR back to the default location, following the
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* procedure specified in the MPC8313 manual.
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*/
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lwz r4, IMMRBAR_BASE(r8)
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isync
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lis r4, DEFAULT_IMMR_VALUE@h
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stw r4, IMMRBAR_BASE(r8)
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lis r4, KERNELBASE@h
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lwz r4, 0(r4)
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isync
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lwz r4, IMMRBAR_BASE(r9)
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mr r8, r9
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isync
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/* Check the Reset Configuration Word to see whether flash needs
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* to be mapped at a low address or a high address.
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*/
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lwz r4, 0x0904(r8)
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andis. r4, r4, 0x0400
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li r4, 0
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beq boot_low
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lis r4, 0xff80
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boot_low:
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stw r4, 0x0020(r8)
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lis r7, 0x8000
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ori r7, r7, 0x0016
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mfspr r5, SPRN_HID0
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rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
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oris r5, r5, HID0_SLEEP@h
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mtspr SPRN_HID0, r5
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isync
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mfmsr r5
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oris r5, r5, MSR_POW@h
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/* Enable the flash mapping at the appropriate address. This
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* mapping will override the RAM mapping if booting low, so there's
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* no need to disable the latter. This must be done inside the same
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* cache line as setting MSR_POW, so that no instruction fetches
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* from RAM happen after the flash mapping is turned on.
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*/
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.align 5
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stw r7, 0x0024(r8)
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sync
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isync
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mtmsr r5
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isync
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1: b 1b
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mpc83xx_deep_resume:
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lis r4, 1f@h
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ori r4, r4, 1f@l
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tophys(r4, r4)
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mtsrr0 r4
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mfmsr r4
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rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
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mtsrr1 r4
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rfi
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1: tlbia
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bl __inval_enable_L1
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lis r3, mpc83xx_sleep_save_area@h
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ori r3, r3, mpc83xx_sleep_save_area@l
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tophys(r3, r3)
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lwz r5, SS_MEMSAVE+0(r3)
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lwz r6, SS_MEMSAVE+4(r3)
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stw r5, 0(0)
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stw r6, 4(0)
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lwz r5, SS_HID+0(r3)
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lwz r6, SS_HID+4(r3)
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lwz r7, SS_HID+8(r3)
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mtspr SPRN_HID0, r5
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mtspr SPRN_HID1, r6
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mtspr SPRN_HID2, r7
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lwz r4, SS_IABR+0(r3)
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lwz r5, SS_IABR+4(r3)
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lwz r6, SS_IBCR(r3)
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lwz r7, SS_DABR+0(r3)
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lwz r8, SS_DABR+4(r3)
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lwz r9, SS_DBCR(r3)
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mtspr SPRN_IABR, r4
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mtspr SPRN_IABR2, r5
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mtspr SPRN_IBCR, r6
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mtspr SPRN_DABR, r7
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mtspr SPRN_DABR2, r8
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mtspr SPRN_DBCR, r9
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li r4, 0
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addi r6, r3, SS_SR-4
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1: lwzu r5, 4(r6)
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mtsrin r5, r4
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addis r4, r4, 0x1000
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cmpwi r4, 0
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bne 1b
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lwz r4, SS_DBAT+0x00(r3)
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lwz r5, SS_DBAT+0x04(r3)
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lwz r6, SS_DBAT+0x08(r3)
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lwz r7, SS_DBAT+0x0c(r3)
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mtspr SPRN_DBAT0U, r4
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||||
mtspr SPRN_DBAT0L, r5
|
||||
mtspr SPRN_DBAT1U, r6
|
||||
mtspr SPRN_DBAT1L, r7
|
||||
|
||||
lwz r4, SS_DBAT+0x10(r3)
|
||||
lwz r5, SS_DBAT+0x14(r3)
|
||||
lwz r6, SS_DBAT+0x18(r3)
|
||||
lwz r7, SS_DBAT+0x1c(r3)
|
||||
|
||||
mtspr SPRN_DBAT2U, r4
|
||||
mtspr SPRN_DBAT2L, r5
|
||||
mtspr SPRN_DBAT3U, r6
|
||||
mtspr SPRN_DBAT3L, r7
|
||||
|
||||
lwz r4, SS_DBAT+0x20(r3)
|
||||
lwz r5, SS_DBAT+0x24(r3)
|
||||
lwz r6, SS_DBAT+0x28(r3)
|
||||
lwz r7, SS_DBAT+0x2c(r3)
|
||||
|
||||
mtspr SPRN_DBAT4U, r4
|
||||
mtspr SPRN_DBAT4L, r5
|
||||
mtspr SPRN_DBAT5U, r6
|
||||
mtspr SPRN_DBAT5L, r7
|
||||
|
||||
lwz r4, SS_DBAT+0x30(r3)
|
||||
lwz r5, SS_DBAT+0x34(r3)
|
||||
lwz r6, SS_DBAT+0x38(r3)
|
||||
lwz r7, SS_DBAT+0x3c(r3)
|
||||
|
||||
mtspr SPRN_DBAT6U, r4
|
||||
mtspr SPRN_DBAT6L, r5
|
||||
mtspr SPRN_DBAT7U, r6
|
||||
mtspr SPRN_DBAT7L, r7
|
||||
|
||||
lwz r4, SS_IBAT+0x00(r3)
|
||||
lwz r5, SS_IBAT+0x04(r3)
|
||||
lwz r6, SS_IBAT+0x08(r3)
|
||||
lwz r7, SS_IBAT+0x0c(r3)
|
||||
|
||||
mtspr SPRN_IBAT0U, r4
|
||||
mtspr SPRN_IBAT0L, r5
|
||||
mtspr SPRN_IBAT1U, r6
|
||||
mtspr SPRN_IBAT1L, r7
|
||||
|
||||
lwz r4, SS_IBAT+0x10(r3)
|
||||
lwz r5, SS_IBAT+0x14(r3)
|
||||
lwz r6, SS_IBAT+0x18(r3)
|
||||
lwz r7, SS_IBAT+0x1c(r3)
|
||||
|
||||
mtspr SPRN_IBAT2U, r4
|
||||
mtspr SPRN_IBAT2L, r5
|
||||
mtspr SPRN_IBAT3U, r6
|
||||
mtspr SPRN_IBAT3L, r7
|
||||
|
||||
lwz r4, SS_IBAT+0x20(r3)
|
||||
lwz r5, SS_IBAT+0x24(r3)
|
||||
lwz r6, SS_IBAT+0x28(r3)
|
||||
lwz r7, SS_IBAT+0x2c(r3)
|
||||
|
||||
mtspr SPRN_IBAT4U, r4
|
||||
mtspr SPRN_IBAT4L, r5
|
||||
mtspr SPRN_IBAT5U, r6
|
||||
mtspr SPRN_IBAT5L, r7
|
||||
|
||||
lwz r4, SS_IBAT+0x30(r3)
|
||||
lwz r5, SS_IBAT+0x34(r3)
|
||||
lwz r6, SS_IBAT+0x38(r3)
|
||||
lwz r7, SS_IBAT+0x3c(r3)
|
||||
|
||||
mtspr SPRN_IBAT6U, r4
|
||||
mtspr SPRN_IBAT6L, r5
|
||||
mtspr SPRN_IBAT7U, r6
|
||||
mtspr SPRN_IBAT7L, r7
|
||||
|
||||
lwz r4, SS_SPRG+0(r3)
|
||||
lwz r5, SS_SPRG+4(r3)
|
||||
lwz r6, SS_SPRG+8(r3)
|
||||
lwz r7, SS_SPRG+12(r3)
|
||||
lwz r8, SS_SDR1(r3)
|
||||
|
||||
mtspr SPRN_SPRG0, r4
|
||||
mtspr SPRN_SPRG1, r5
|
||||
mtspr SPRN_SPRG2, r6
|
||||
mtspr SPRN_SPRG3, r7
|
||||
mtsdr1 r8
|
||||
|
||||
lwz r4, SS_MSR(r3)
|
||||
lwz r5, SS_LR(r3)
|
||||
lwz r6, SS_CR(r3)
|
||||
lwz r1, SS_SP(r3)
|
||||
lwz r2, SS_R2(r3)
|
||||
|
||||
mtsrr1 r4
|
||||
mtsrr0 r5
|
||||
mtcr r6
|
||||
|
||||
li r4, 0
|
||||
mtspr SPRN_TBWL, r4
|
||||
|
||||
lwz r4, SS_TB+0(r3)
|
||||
lwz r5, SS_TB+4(r3)
|
||||
|
||||
mtspr SPRN_TBWU, r4
|
||||
mtspr SPRN_TBWL, r5
|
||||
|
||||
lmw r12, SS_GPREG(r3)
|
||||
|
||||
/* Kick decrementer */
|
||||
li r0, 1
|
||||
mtdec r0
|
||||
|
||||
rfi
|
||||
388
arch/powerpc/platforms/83xx/suspend.c
Normal file
388
arch/powerpc/platforms/83xx/suspend.c
Normal file
@ -0,0 +1,388 @@
|
||||
/*
|
||||
* MPC83xx suspend support
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/freezer.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/fsl_devices.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/reg.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mpc6xx.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
|
||||
#define PMCCR1_NEXT_STATE_SHIFT 2
|
||||
#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
|
||||
#define IMMR_RCW_OFFSET 0x900
|
||||
#define RCW_PCI_HOST 0x80000000
|
||||
|
||||
void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
|
||||
|
||||
struct mpc83xx_pmc {
|
||||
u32 config;
|
||||
#define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
|
||||
#define PMCCR_SLPEN 1 /* System low power enable */
|
||||
|
||||
u32 event;
|
||||
u32 mask;
|
||||
/* All but PMCI are deep-sleep only */
|
||||
#define PMCER_GPIO 0x100
|
||||
#define PMCER_PCI 0x080
|
||||
#define PMCER_USB 0x040
|
||||
#define PMCER_ETSEC1 0x020
|
||||
#define PMCER_ETSEC2 0x010
|
||||
#define PMCER_TIMER 0x008
|
||||
#define PMCER_INT1 0x004
|
||||
#define PMCER_INT2 0x002
|
||||
#define PMCER_PMCI 0x001
|
||||
#define PMCER_ALL 0x1FF
|
||||
|
||||
/* deep-sleep only */
|
||||
u32 config1;
|
||||
#define PMCCR1_USE_STATE 0x80000000
|
||||
#define PMCCR1_PME_EN 0x00000080
|
||||
#define PMCCR1_ASSERT_PME 0x00000040
|
||||
#define PMCCR1_POWER_OFF 0x00000020
|
||||
|
||||
/* deep-sleep only */
|
||||
u32 config2;
|
||||
};
|
||||
|
||||
struct mpc83xx_rcw {
|
||||
u32 rcwlr;
|
||||
u32 rcwhr;
|
||||
};
|
||||
|
||||
struct mpc83xx_clock {
|
||||
u32 spmr;
|
||||
u32 occr;
|
||||
u32 sccr;
|
||||
};
|
||||
|
||||
struct pmc_type {
|
||||
int has_deep_sleep;
|
||||
};
|
||||
|
||||
static struct of_device *pmc_dev;
|
||||
static int has_deep_sleep, deep_sleeping;
|
||||
static int pmc_irq;
|
||||
static struct mpc83xx_pmc __iomem *pmc_regs;
|
||||
static struct mpc83xx_clock __iomem *clock_regs;
|
||||
static int is_pci_agent, wake_from_pci;
|
||||
static phys_addr_t immrbase;
|
||||
static int pci_pm_state;
|
||||
static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
|
||||
|
||||
int fsl_deep_sleep(void)
|
||||
{
|
||||
return deep_sleeping;
|
||||
}
|
||||
|
||||
static int mpc83xx_change_state(void)
|
||||
{
|
||||
u32 curr_state;
|
||||
u32 reg_cfg1 = in_be32(&pmc_regs->config1);
|
||||
|
||||
if (is_pci_agent) {
|
||||
pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
|
||||
PMCCR1_NEXT_STATE_SHIFT;
|
||||
curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
|
||||
|
||||
if (curr_state != pci_pm_state) {
|
||||
reg_cfg1 &= ~PMCCR1_CURR_STATE;
|
||||
reg_cfg1 |= pci_pm_state;
|
||||
out_be32(&pmc_regs->config1, reg_cfg1);
|
||||
|
||||
wake_up(&agent_wq);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
u32 event = in_be32(&pmc_regs->event);
|
||||
int ret = IRQ_NONE;
|
||||
|
||||
if (mpc83xx_change_state())
|
||||
ret = IRQ_HANDLED;
|
||||
|
||||
if (event) {
|
||||
out_be32(&pmc_regs->event, event);
|
||||
ret = IRQ_HANDLED;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mpc83xx_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
int ret = -EAGAIN;
|
||||
|
||||
/* Don't go to sleep if there's a race where pci_pm_state changes
|
||||
* between the agent thread checking it and the PM code disabling
|
||||
* interrupts.
|
||||
*/
|
||||
if (wake_from_pci) {
|
||||
if (pci_pm_state != (deep_sleeping ? 3 : 2))
|
||||
goto out;
|
||||
|
||||
out_be32(&pmc_regs->config1,
|
||||
in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
|
||||
}
|
||||
|
||||
/* Put the system into low-power mode and the RAM
|
||||
* into self-refresh mode once the core goes to
|
||||
* sleep.
|
||||
*/
|
||||
|
||||
out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
|
||||
|
||||
/* If it has deep sleep (i.e. it's an 831x or compatible),
|
||||
* disable power to the core upon entering sleep mode. This will
|
||||
* require going through the boot firmware upon a wakeup event.
|
||||
*/
|
||||
|
||||
if (deep_sleeping) {
|
||||
out_be32(&pmc_regs->mask, PMCER_ALL);
|
||||
|
||||
out_be32(&pmc_regs->config1,
|
||||
in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
|
||||
|
||||
enable_kernel_fp();
|
||||
|
||||
mpc83xx_enter_deep_sleep(immrbase);
|
||||
|
||||
out_be32(&pmc_regs->config1,
|
||||
in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
|
||||
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
} else {
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
mpc6xx_enter_standby();
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
out_be32(&pmc_regs->config1,
|
||||
in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mpc83xx_suspend_finish(void)
|
||||
{
|
||||
deep_sleeping = 0;
|
||||
}
|
||||
|
||||
static int mpc83xx_suspend_valid(suspend_state_t state)
|
||||
{
|
||||
return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
|
||||
}
|
||||
|
||||
static int mpc83xx_suspend_begin(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
deep_sleeping = 0;
|
||||
return 0;
|
||||
|
||||
case PM_SUSPEND_MEM:
|
||||
if (has_deep_sleep)
|
||||
deep_sleeping = 1;
|
||||
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int agent_thread_fn(void *data)
|
||||
{
|
||||
while (1) {
|
||||
wait_event_interruptible(agent_wq, pci_pm_state >= 2);
|
||||
try_to_freeze();
|
||||
|
||||
if (signal_pending(current) || pci_pm_state < 2)
|
||||
continue;
|
||||
|
||||
/* With a preemptible kernel (or SMP), this could race with
|
||||
* a userspace-driven suspend request. It's probably best
|
||||
* to avoid mixing the two with such a configuration (or
|
||||
* else fix it by adding a mutex to state_store that we can
|
||||
* synchronize with).
|
||||
*/
|
||||
|
||||
wake_from_pci = 1;
|
||||
|
||||
pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
|
||||
PM_SUSPEND_STANDBY);
|
||||
|
||||
wake_from_pci = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpc83xx_set_agent(void)
|
||||
{
|
||||
out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
kthread_run(agent_thread_fn, NULL, "PCI power mgt");
|
||||
}
|
||||
|
||||
static int mpc83xx_is_pci_agent(void)
|
||||
{
|
||||
struct mpc83xx_rcw __iomem *rcw_regs;
|
||||
int ret;
|
||||
|
||||
rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
|
||||
sizeof(struct mpc83xx_rcw));
|
||||
|
||||
if (!rcw_regs)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
|
||||
|
||||
iounmap(rcw_regs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops mpc83xx_suspend_ops = {
|
||||
.valid = mpc83xx_suspend_valid,
|
||||
.begin = mpc83xx_suspend_begin,
|
||||
.enter = mpc83xx_suspend_enter,
|
||||
.finish = mpc83xx_suspend_finish,
|
||||
};
|
||||
|
||||
static int pmc_probe(struct of_device *ofdev,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
struct device_node *np = ofdev->node;
|
||||
struct resource res;
|
||||
struct pmc_type *type = match->data;
|
||||
int ret = 0;
|
||||
|
||||
if (!of_device_is_available(np))
|
||||
return -ENODEV;
|
||||
|
||||
has_deep_sleep = type->has_deep_sleep;
|
||||
immrbase = get_immrbase();
|
||||
pmc_dev = ofdev;
|
||||
|
||||
is_pci_agent = mpc83xx_is_pci_agent();
|
||||
if (is_pci_agent < 0)
|
||||
return is_pci_agent;
|
||||
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
if (ret)
|
||||
return -ENODEV;
|
||||
|
||||
pmc_irq = irq_of_parse_and_map(np, 0);
|
||||
if (pmc_irq != NO_IRQ) {
|
||||
ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
|
||||
"pmc", ofdev);
|
||||
|
||||
if (ret)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
|
||||
|
||||
if (!pmc_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = of_address_to_resource(np, 1, &res);
|
||||
if (ret) {
|
||||
ret = -ENODEV;
|
||||
goto out_pmc;
|
||||
}
|
||||
|
||||
clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
|
||||
|
||||
if (!clock_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto out_pmc;
|
||||
}
|
||||
|
||||
if (is_pci_agent)
|
||||
mpc83xx_set_agent();
|
||||
|
||||
suspend_set_ops(&mpc83xx_suspend_ops);
|
||||
return 0;
|
||||
|
||||
out_pmc:
|
||||
iounmap(pmc_regs);
|
||||
out:
|
||||
if (pmc_irq != NO_IRQ)
|
||||
free_irq(pmc_irq, ofdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pmc_remove(struct of_device *ofdev)
|
||||
{
|
||||
return -EPERM;
|
||||
};
|
||||
|
||||
static struct pmc_type pmc_types[] = {
|
||||
{
|
||||
.has_deep_sleep = 1,
|
||||
},
|
||||
{
|
||||
.has_deep_sleep = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct of_device_id pmc_match[] = {
|
||||
{
|
||||
.compatible = "fsl,mpc8313-pmc",
|
||||
.data = &pmc_types[0],
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,mpc8349-pmc",
|
||||
.data = &pmc_types[1],
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct of_platform_driver pmc_driver = {
|
||||
.name = "mpc83xx-pmc",
|
||||
.match_table = pmc_match,
|
||||
.probe = pmc_probe,
|
||||
.remove = pmc_remove
|
||||
};
|
||||
|
||||
static int pmc_init(void)
|
||||
{
|
||||
return of_register_platform_driver(&pmc_driver);
|
||||
}
|
||||
|
||||
module_init(pmc_init);
|
||||
@ -10,6 +10,7 @@ extern u32 get_baudrate(void);
|
||||
extern u32 fsl_get_sys_freq(void);
|
||||
|
||||
struct spi_board_info;
|
||||
struct device_node;
|
||||
|
||||
extern int fsl_spi_init(struct spi_board_info *board_infos,
|
||||
unsigned int num_board_infos,
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include <linux/device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/fsl_devices.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/prom.h>
|
||||
@ -889,8 +890,78 @@ unsigned int ipic_get_irq(void)
|
||||
return irq_linear_revmap(primary_ipic->irqhost, irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static struct {
|
||||
u32 sicfr;
|
||||
u32 siprr[2];
|
||||
u32 simsr[2];
|
||||
u32 sicnr;
|
||||
u32 smprr[2];
|
||||
u32 semsr;
|
||||
u32 secnr;
|
||||
u32 sermr;
|
||||
u32 sercr;
|
||||
} ipic_saved_state;
|
||||
|
||||
static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
|
||||
{
|
||||
struct ipic *ipic = primary_ipic;
|
||||
|
||||
ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
|
||||
ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
|
||||
ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
|
||||
ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
|
||||
ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
|
||||
ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
|
||||
ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
|
||||
ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
|
||||
ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
|
||||
ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
|
||||
ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
|
||||
ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
|
||||
|
||||
if (fsl_deep_sleep()) {
|
||||
/* In deep sleep, make sure there can be no
|
||||
* pending interrupts, as this can cause
|
||||
* problems on 831x.
|
||||
*/
|
||||
ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
|
||||
ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
|
||||
ipic_write(ipic->regs, IPIC_SEMSR, 0);
|
||||
ipic_write(ipic->regs, IPIC_SERMR, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ipic_resume(struct sys_device *sdev)
|
||||
{
|
||||
struct ipic *ipic = primary_ipic;
|
||||
|
||||
ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
|
||||
ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
|
||||
ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
|
||||
ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
|
||||
ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
|
||||
ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
|
||||
ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
|
||||
ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
|
||||
ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
|
||||
ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
|
||||
ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
|
||||
ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define ipic_suspend NULL
|
||||
#define ipic_resume NULL
|
||||
#endif
|
||||
|
||||
static struct sysdev_class ipic_sysclass = {
|
||||
.name = "ipic",
|
||||
.suspend = ipic_suspend,
|
||||
.resume = ipic_resume,
|
||||
};
|
||||
|
||||
static struct sys_device device_ipic = {
|
||||
|
||||
@ -155,10 +155,12 @@
|
||||
#define CTRL_RUNLATCH 0x1
|
||||
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
|
||||
#define DABR_TRANSLATION (1UL << 2)
|
||||
#define SPRN_DABR2 0x13D /* e300 */
|
||||
#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
|
||||
#define DABRX_USER (1UL << 0)
|
||||
#define DABRX_KERNEL (1UL << 1)
|
||||
#define SPRN_DAR 0x013 /* Data Address Register */
|
||||
#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
|
||||
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
|
||||
#define DSISR_NOHPTE 0x40000000 /* no translation found */
|
||||
#define DSISR_PROTFAULT 0x08000000 /* protection fault */
|
||||
@ -264,6 +266,8 @@
|
||||
#define HID1_PS (1<<16) /* 750FX PLL selection */
|
||||
#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
|
||||
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
|
||||
#define SPRN_IABR2 0x3FA /* 83xx */
|
||||
#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
|
||||
#define SPRN_HID4 0x3F4 /* 970 HID4 */
|
||||
#define SPRN_HID5 0x3F6 /* 970 HID5 */
|
||||
#define SPRN_HID6 0x3F9 /* BE HID 6 */
|
||||
|
||||
@ -125,4 +125,10 @@ struct mpc8xx_pcmcia_ops {
|
||||
int(*voltage_set)(int slot, int vcc, int vpp);
|
||||
};
|
||||
|
||||
/* Returns non-zero if the current suspend operation would
|
||||
* lead to a deep sleep (i.e. power removed from the core,
|
||||
* instead of just the clock).
|
||||
*/
|
||||
int fsl_deep_sleep(void);
|
||||
|
||||
#endif /* _FSL_DEVICE_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user