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sh: clkfwk: clock-sh73a0: all div6_clks use SH_CLK_DIV6_EXT()
Current div6 clocks can specify their current parent clocks from its register value if it is registered by sh_clk_div6_reparent_register(). This patch modifies all div6 clocks into SH_CLK_DIV6_EXT(). Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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171f1bc77c
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@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
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.recalc = div2_recalc,
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.recalc = div2_recalc,
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};
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};
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static unsigned long div7_recalc(struct clk *clk)
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{
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return clk->parent->rate / 7;
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}
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static struct clk_ops div7_clk_ops = {
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.recalc = div7_recalc,
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};
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static unsigned long div13_recalc(struct clk *clk)
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{
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return clk->parent->rate / 13;
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}
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static struct clk_ops div13_clk_ops = {
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.recalc = div13_recalc,
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};
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/* Divide extal1 by two */
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/* Divide extal1 by two */
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static struct clk extal1_div2_clk = {
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static struct clk extal1_div2_clk = {
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.ops = &div2_clk_ops,
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.ops = &div2_clk_ops,
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@ -113,6 +131,11 @@ static struct clk main_clk = {
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.ops = &main_clk_ops,
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.ops = &main_clk_ops,
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};
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};
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static struct clk main_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &main_clk,
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};
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/* PLL0, PLL1, PLL2, PLL3 */
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/* PLL0, PLL1, PLL2, PLL3 */
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static unsigned long pll_recalc(struct clk *clk)
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static unsigned long pll_recalc(struct clk *clk)
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{
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{
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@ -168,12 +191,29 @@ static struct clk pll3_clk = {
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.enable_bit = 3,
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.enable_bit = 3,
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};
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};
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/* Divide PLL1 by two */
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/* Divide PLL */
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static struct clk pll1_div2_clk = {
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static struct clk pll1_div2_clk = {
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.ops = &div2_clk_ops,
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.ops = &div2_clk_ops,
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.parent = &pll1_clk,
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.parent = &pll1_clk,
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};
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};
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static struct clk pll1_div7_clk = {
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.ops = &div7_clk_ops,
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.parent = &pll1_clk,
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};
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static struct clk pll1_div13_clk = {
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.ops = &div13_clk_ops,
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.parent = &pll1_clk,
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};
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/* External input clock */
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struct clk sh73a0_extcki_clk = {
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};
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struct clk sh73a0_extalr_clk = {
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};
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static struct clk *main_clks[] = {
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static struct clk *main_clks[] = {
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&r_clk,
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&r_clk,
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&sh73a0_extal1_clk,
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&sh73a0_extal1_clk,
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@ -181,11 +221,16 @@ static struct clk *main_clks[] = {
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&extal1_div2_clk,
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&extal1_div2_clk,
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&extal2_div2_clk,
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&extal2_div2_clk,
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&main_clk,
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&main_clk,
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&main_div2_clk,
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&pll0_clk,
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&pll0_clk,
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&pll1_clk,
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&pll1_clk,
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&pll2_clk,
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&pll2_clk,
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&pll3_clk,
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&pll3_clk,
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&pll1_div2_clk,
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&pll1_div2_clk,
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&pll1_div7_clk,
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&pll1_div13_clk,
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&sh73a0_extcki_clk,
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&sh73a0_extalr_clk,
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};
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};
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static void div4_kick(struct clk *clk)
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static void div4_kick(struct clk *clk)
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@ -239,27 +284,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
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DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_NR };
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DIV6_NR };
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static struct clk *vck_parent[8] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &sh73a0_extcki_clk,
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[3] = &sh73a0_extal2_clk,
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[4] = &main_div2_clk,
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[5] = &sh73a0_extalr_clk,
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[6] = &main_clk,
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};
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static struct clk *pll_parent[4] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &pll1_div13_clk,
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};
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static struct clk *hsi_parent[4] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &pll1_div7_clk,
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};
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static struct clk *pll_extal2_parent[] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &sh73a0_extal2_clk,
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[3] = &sh73a0_extal2_clk,
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};
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static struct clk *dsi_parent[8] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &main_clk,
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[3] = &sh73a0_extal2_clk,
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[4] = &sh73a0_extcki_clk,
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};
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static struct clk div6_clks[DIV6_NR] = {
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
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[DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
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[DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
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[DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
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[DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
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[DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
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[DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
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[DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, 0,
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[DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
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[DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
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[DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
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[DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
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[DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
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[DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
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[DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
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[DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
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[DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
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[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
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[DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
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[DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
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[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
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[DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
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pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
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[DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
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hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
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[DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
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dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
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[DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
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dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
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};
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};
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enum { MSTP001,
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enum { MSTP001,
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@ -387,7 +489,7 @@ void __init sh73a0_clock_init(void)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
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if (!ret)
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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@ -47,6 +47,8 @@ extern void sh73a0_clock_init(void);
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extern void sh73a0_pinmux_init(void);
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extern void sh73a0_pinmux_init(void);
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extern struct clk sh73a0_extal1_clk;
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extern struct clk sh73a0_extal1_clk;
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extern struct clk sh73a0_extal2_clk;
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extern struct clk sh73a0_extal2_clk;
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extern struct clk sh73a0_extcki_clk;
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extern struct clk sh73a0_extalr_clk;
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extern unsigned int sh73a0_get_core_count(void);
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extern unsigned int sh73a0_get_core_count(void);
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extern void sh73a0_secondary_init(unsigned int cpu);
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extern void sh73a0_secondary_init(unsigned int cpu);
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