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MIPS: BCM63XX: Add more register sets & missing register definitions.
Needed for upcoming 6368 CPU support. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2893/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maxime Bizon
Ralf Baechle
parent
ec68c5206a
commit
d430b6c5e7
@ -88,6 +88,7 @@ enum bcm63xx_regs_set {
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RSET_UART1,
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RSET_GPIO,
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RSET_SPI,
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RSET_SPI2,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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@ -98,10 +99,23 @@ enum bcm63xx_regs_set {
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RSET_ENET0,
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RSET_ENET1,
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RSET_ENETDMA,
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RSET_ENETDMAC,
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RSET_ENETDMAS,
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RSET_ENETSW,
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RSET_EHCI0,
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RSET_SDRAM,
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RSET_MEMC,
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RSET_DDR,
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RSET_M2M,
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RSET_ATM,
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RSET_XTM,
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RSET_XTMDMA,
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RSET_XTMDMAC,
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RSET_XTMDMAS,
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RSET_PCM,
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RSET_PCMDMA,
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@ -109,11 +123,18 @@ enum bcm63xx_regs_set {
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#define RSET_WDT_SIZE 12
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_ENETSW_SIZE 65536
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#define RSET_UART_SIZE 24
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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#define RSET_PCMCIA_SIZE 12
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#define RSET_M2M_SIZE 256
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#define RSET_ATM_SIZE 4096
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#define RSET_XTM_SIZE 10240
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#define RSET_XTMDMA_SIZE 256
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#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
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#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
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/*
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* 6338 register sets base address
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@ -127,6 +148,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_SPI2_BASE (0xdeadbeef)
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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@ -136,15 +158,27 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_SAR_BASE (0xfffe2000)
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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#define BCM_6338_ENET0_BASE (0xfffe2800)
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#define BCM_6338_ENET1_BASE (0xdeadbeef)
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#define BCM_6338_ENETDMA_BASE (0xfffe2400)
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#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
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#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
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#define BCM_6338_ENETSW_BASE (0xdeadbeef)
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#define BCM_6338_EHCI0_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_BASE (0xfffe3100)
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#define BCM_6338_MEMC_BASE (0xdeadbeef)
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#define BCM_6338_DDR_BASE (0xdeadbeef)
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#define BCM_6338_M2M_BASE (0xdeadbeef)
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#define BCM_6338_ATM_BASE (0xfffe2000)
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#define BCM_6338_XTM_BASE (0xdeadbeef)
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#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
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#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_PCM_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@ -158,10 +192,14 @@ enum bcm63xx_regs_set {
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#define BCM_6345_UART1_BASE (0xdeadbeef)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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#define BCM_6345_SPI_BASE (0xdeadbeef)
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#define BCM_6345_SPI2_BASE (0xdeadbeef)
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#define BCM_6345_UDC0_BASE (0xdeadbeef)
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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#define BCM_6345_ENETDMA_BASE (0xfffe2800)
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#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
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#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xdeadbeef)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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@ -169,13 +207,22 @@ enum bcm63xx_regs_set {
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6345_DSL_BASE (0xdeadbeef)
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#define BCM_6345_SAR_BASE (0xdeadbeef)
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#define BCM_6345_UBUS_BASE (0xdeadbeef)
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#define BCM_6345_ENET1_BASE (0xdeadbeef)
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#define BCM_6345_EHCI0_BASE (0xdeadbeef)
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#define BCM_6345_SDRAM_BASE (0xfffe2300)
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#define BCM_6345_MEMC_BASE (0xdeadbeef)
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#define BCM_6345_DDR_BASE (0xdeadbeef)
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#define BCM_6345_M2M_BASE (0xdeadbeef)
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#define BCM_6345_ATM_BASE (0xfffe4000)
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#define BCM_6345_XTM_BASE (0xdeadbeef)
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#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
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#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_PCM_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@ -188,6 +235,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_UART1_BASE (0xdeadbeef)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_SPI2_BASE (0xdeadbeef)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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@ -195,14 +243,27 @@ enum bcm63xx_regs_set {
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_M2M_BASE (0xfffe2800)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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#define BCM_6348_ENET0_BASE (0xfffe6000)
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#define BCM_6348_ENET1_BASE (0xfffe6800)
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#define BCM_6348_ENETDMA_BASE (0xfffe7000)
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#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
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#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
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#define BCM_6348_ENETSW_BASE (0xdeadbeef)
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#define BCM_6348_EHCI0_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_BASE (0xfffe2300)
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#define BCM_6348_MEMC_BASE (0xdeadbeef)
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#define BCM_6348_DDR_BASE (0xdeadbeef)
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#define BCM_6348_ATM_BASE (0xfffe4000)
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#define BCM_6348_XTM_BASE (0xdeadbeef)
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#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
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#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_PCM_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@ -215,6 +276,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_UART1_BASE (0xfffe0120)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xdeadbeef)
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#define BCM_6358_SPI2_BASE (0xfffe0800)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
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@ -222,14 +284,28 @@ enum bcm63xx_regs_set {
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_M2M_BASE (0xdeadbeef)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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#define BCM_6358_ENET0_BASE (0xfffe4000)
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#define BCM_6358_ENET1_BASE (0xfffe4800)
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#define BCM_6358_ENETDMA_BASE (0xfffe5000)
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#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
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#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
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#define BCM_6358_ENETSW_BASE (0xdeadbeef)
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#define BCM_6358_EHCI0_BASE (0xfffe1300)
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#define BCM_6358_SDRAM_BASE (0xdeadbeef)
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#define BCM_6358_MEMC_BASE (0xfffe1200)
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#define BCM_6358_DDR_BASE (0xfffe12a0)
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#define BCM_6358_ATM_BASE (0xfffe2000)
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#define BCM_6358_XTM_BASE (0xdeadbeef)
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#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
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#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6358_PCM_BASE (0xfffe1600)
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#define BCM_6358_PCMDMA_BASE (0xfffe1800)
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#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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extern const unsigned long *bcm63xx_regs_base;
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@ -248,6 +324,7 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, UART1) \
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__GEN_RSET_BASE(__cpu, GPIO) \
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__GEN_RSET_BASE(__cpu, SPI) \
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__GEN_RSET_BASE(__cpu, SPI2) \
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__GEN_RSET_BASE(__cpu, UDC0) \
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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@ -258,10 +335,23 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, ENET0) \
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__GEN_RSET_BASE(__cpu, ENET1) \
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__GEN_RSET_BASE(__cpu, ENETDMA) \
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__GEN_RSET_BASE(__cpu, ENETDMAC) \
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__GEN_RSET_BASE(__cpu, ENETDMAS) \
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__GEN_RSET_BASE(__cpu, ENETSW) \
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__GEN_RSET_BASE(__cpu, EHCI0) \
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__GEN_RSET_BASE(__cpu, SDRAM) \
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__GEN_RSET_BASE(__cpu, MEMC) \
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__GEN_RSET_BASE(__cpu, DDR) \
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__GEN_RSET_BASE(__cpu, M2M) \
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__GEN_RSET_BASE(__cpu, ATM) \
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__GEN_RSET_BASE(__cpu, XTM) \
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__GEN_RSET_BASE(__cpu, XTMDMA) \
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__GEN_RSET_BASE(__cpu, XTMDMAC) \
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__GEN_RSET_BASE(__cpu, XTMDMAS) \
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__GEN_RSET_BASE(__cpu, PCM) \
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__GEN_RSET_BASE(__cpu, PCMDMA) \
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__GEN_RSET_BASE(__cpu, PCMDMAC) \
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__GEN_RSET_BASE(__cpu, PCMDMAS) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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@ -273,6 +363,7 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
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[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
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[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
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[RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
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[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
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[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
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[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
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@ -283,10 +374,23 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
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[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
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[RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
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[RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
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[RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
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[RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
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[RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
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[RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
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[RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
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[RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
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[RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
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[RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
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[RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
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[RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
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[RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
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[RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
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[RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
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[RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
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[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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@ -330,6 +434,17 @@ enum bcm63xx_irq {
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IRQ_ENET1_TXDMA,
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IRQ_PCI,
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IRQ_PCMCIA,
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IRQ_ATM,
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IRQ_ENETSW_RXDMA0,
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IRQ_ENETSW_RXDMA1,
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IRQ_ENETSW_RXDMA2,
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IRQ_ENETSW_RXDMA3,
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IRQ_ENETSW_TXDMA0,
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IRQ_ENETSW_TXDMA1,
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IRQ_ENETSW_TXDMA2,
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IRQ_ENETSW_TXDMA3,
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IRQ_XTM,
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IRQ_XTM_DMA0,
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};
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/*
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@ -350,6 +465,17 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET1_TXDMA_IRQ 0
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#define BCM_6338_PCI_IRQ 0
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#define BCM_6338_PCMCIA_IRQ 0
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#define BCM_6338_ATM_IRQ 0
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#define BCM_6338_ENETSW_RXDMA0_IRQ 0
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#define BCM_6338_ENETSW_RXDMA1_IRQ 0
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#define BCM_6338_ENETSW_RXDMA2_IRQ 0
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#define BCM_6338_ENETSW_RXDMA3_IRQ 0
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#define BCM_6338_ENETSW_TXDMA0_IRQ 0
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#define BCM_6338_ENETSW_TXDMA1_IRQ 0
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#define BCM_6338_ENETSW_TXDMA2_IRQ 0
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#define BCM_6338_ENETSW_TXDMA3_IRQ 0
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#define BCM_6338_XTM_IRQ 0
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#define BCM_6338_XTM_DMA0_IRQ 0
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/*
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* 6345 irqs
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@ -369,6 +495,17 @@ enum bcm63xx_irq {
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#define BCM_6345_ENET1_TXDMA_IRQ 0
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#define BCM_6345_PCI_IRQ 0
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#define BCM_6345_PCMCIA_IRQ 0
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#define BCM_6345_ATM_IRQ 0
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#define BCM_6345_ENETSW_RXDMA0_IRQ 0
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#define BCM_6345_ENETSW_RXDMA1_IRQ 0
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#define BCM_6345_ENETSW_RXDMA2_IRQ 0
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#define BCM_6345_ENETSW_RXDMA3_IRQ 0
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#define BCM_6345_ENETSW_TXDMA0_IRQ 0
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#define BCM_6345_ENETSW_TXDMA1_IRQ 0
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#define BCM_6345_ENETSW_TXDMA2_IRQ 0
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#define BCM_6345_ENETSW_TXDMA3_IRQ 0
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#define BCM_6345_XTM_IRQ 0
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#define BCM_6345_XTM_DMA0_IRQ 0
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/*
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* 6348 irqs
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@ -388,6 +525,17 @@ enum bcm63xx_irq {
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#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
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#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
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#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
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#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6348_ENETSW_RXDMA0_IRQ 0
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#define BCM_6348_ENETSW_RXDMA1_IRQ 0
|
||||
#define BCM_6348_ENETSW_RXDMA2_IRQ 0
|
||||
#define BCM_6348_ENETSW_RXDMA3_IRQ 0
|
||||
#define BCM_6348_ENETSW_TXDMA0_IRQ 0
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||||
#define BCM_6348_ENETSW_TXDMA1_IRQ 0
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||||
#define BCM_6348_ENETSW_TXDMA2_IRQ 0
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||||
#define BCM_6348_ENETSW_TXDMA3_IRQ 0
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#define BCM_6348_XTM_IRQ 0
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||||
#define BCM_6348_XTM_DMA0_IRQ 0
|
||||
|
||||
/*
|
||||
* 6358 irqs
|
||||
@ -407,6 +555,24 @@ enum bcm63xx_irq {
|
||||
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
|
||||
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
|
||||
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
|
||||
#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
|
||||
#define BCM_6358_ENETSW_RXDMA0_IRQ 0
|
||||
#define BCM_6358_ENETSW_RXDMA1_IRQ 0
|
||||
#define BCM_6358_ENETSW_RXDMA2_IRQ 0
|
||||
#define BCM_6358_ENETSW_RXDMA3_IRQ 0
|
||||
#define BCM_6358_ENETSW_TXDMA0_IRQ 0
|
||||
#define BCM_6358_ENETSW_TXDMA1_IRQ 0
|
||||
#define BCM_6358_ENETSW_TXDMA2_IRQ 0
|
||||
#define BCM_6358_ENETSW_TXDMA3_IRQ 0
|
||||
#define BCM_6358_XTM_IRQ 0
|
||||
#define BCM_6358_XTM_DMA0_IRQ 0
|
||||
|
||||
#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
|
||||
#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
|
||||
#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
|
||||
#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
|
||||
#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
|
||||
#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
|
||||
|
||||
extern const int *bcm63xx_irqs;
|
||||
|
||||
@ -426,6 +592,17 @@ extern const int *bcm63xx_irqs;
|
||||
[IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
|
||||
[IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
|
||||
[IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
|
||||
[IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
|
||||
[IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
|
||||
[IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
|
||||
[IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
|
||||
[IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
|
||||
[IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
|
||||
[IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
|
||||
[IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
|
||||
[IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
|
||||
[IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
|
||||
[IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
|
||||
|
||||
static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
|
||||
{
|
||||
@ -437,4 +614,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
|
||||
*/
|
||||
unsigned int bcm63xx_get_memory_size(void);
|
||||
|
||||
void bcm63xx_machine_halt(void);
|
||||
|
||||
void bcm63xx_machine_reboot(void);
|
||||
|
||||
#endif /* !BCM63XX_CPU_H_ */
|
||||
|
||||
@ -547,6 +547,56 @@
|
||||
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_ENETDMAC
|
||||
*************************************************************************/
|
||||
|
||||
/* Channel Configuration register */
|
||||
#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
|
||||
#define ENETDMAC_CHANCFG_EN_SHIFT 0
|
||||
#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
|
||||
#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
|
||||
#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
|
||||
|
||||
/* Interrupt Control/Status register */
|
||||
#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
|
||||
#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
|
||||
#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
|
||||
#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
|
||||
|
||||
/* Interrupt Mask register */
|
||||
#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
|
||||
|
||||
/* Maximum Burst Length */
|
||||
#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_ENETDMAS
|
||||
*************************************************************************/
|
||||
|
||||
/* Ring Start Address register */
|
||||
#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
|
||||
|
||||
/* State Ram Word 2 */
|
||||
#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
|
||||
|
||||
/* State Ram Word 3 */
|
||||
#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
|
||||
|
||||
/* State Ram Word 4 */
|
||||
#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_ENETSW
|
||||
*************************************************************************/
|
||||
|
||||
/* MIB register */
|
||||
#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
|
||||
#define ENETSW_MIB_REG_COUNT 47
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_OHCI_PRIV
|
||||
*************************************************************************/
|
||||
@ -768,4 +818,32 @@
|
||||
#define DMIPSPLLCFG_N2_SHIFT 29
|
||||
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_M2M
|
||||
*************************************************************************/
|
||||
|
||||
#define M2M_RX 0
|
||||
#define M2M_TX 1
|
||||
|
||||
#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
|
||||
#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
|
||||
#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
|
||||
|
||||
#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
|
||||
#define M2M_CTRL_ENABLE_MASK (1 << 0)
|
||||
#define M2M_CTRL_IRQEN_MASK (1 << 1)
|
||||
#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
|
||||
#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
|
||||
#define M2M_CTRL_NOINC_MASK (1 << 8)
|
||||
#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
|
||||
#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
|
||||
#define M2M_CTRL_ENDIAN_MASK (1 << 11)
|
||||
|
||||
#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
|
||||
#define M2M_STAT_DONE (1 << 0)
|
||||
#define M2M_STAT_ERROR (1 << 1)
|
||||
|
||||
#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
|
||||
#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
|
||||
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user