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riscv: fix scratch register clearing in M-mode.

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This patch fixes that the sscratch register clearing in M-mode. It cleared
sscratch register in M-mode, but it should clear mscratch register. That will
cause kernel trap if the CPU core doesn't support S-mode when trying to access
sscratch.

Fixes: 9e80635619 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Greentime Hu 2019-12-19 14:44:59 +08:00 committed by Paul Walmsley
parent 0312a3d4b4
commit d411cf02ed
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/kernel/head.S
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@ -246,7 +246,7 @@ ENTRY(reset_regs)
li t4, 0
li t5, 0
li t6, 0
csrw sscratch, 0
csrw CSR_SCRATCH, 0
#ifdef CONFIG_FPU
csrr t0, CSR_MISA