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Merge branch 'pci/jiang-acpiphp' into next
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commit
d3ce52f50c
@ -115,6 +115,35 @@ static const struct acpi_dock_ops acpiphp_dock_ops = {
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.handler = handle_hotplug_event_func,
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};
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/* Check whether the PCI device is managed by native PCIe hotplug driver */
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static bool device_is_managed_by_native_pciehp(struct pci_dev *pdev)
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{
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u32 reg32;
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acpi_handle tmp;
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struct acpi_pci_root *root;
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/* Check whether the PCIe port supports native PCIe hotplug */
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if (pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32))
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return false;
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if (!(reg32 & PCI_EXP_SLTCAP_HPC))
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return false;
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/*
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* Check whether native PCIe hotplug has been enabled for
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* this PCIe hierarchy.
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*/
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tmp = acpi_find_root_bridge_handle(pdev);
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if (!tmp)
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return false;
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root = acpi_pci_find_root(tmp);
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if (!root)
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return false;
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if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
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return false;
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return true;
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}
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/* callback routine to register each ACPI PCI slot object */
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static acpi_status
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register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
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@ -142,16 +171,8 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
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function = adr & 0xffff;
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pdev = pbus->self;
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if (pdev && pci_is_pcie(pdev)) {
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tmp = acpi_find_root_bridge_handle(pdev);
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if (tmp) {
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struct acpi_pci_root *root = acpi_pci_find_root(tmp);
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if (root && (root->osc_control_set &
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OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
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return AE_OK;
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}
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}
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if (pdev && device_is_managed_by_native_pciehp(pdev))
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return AE_OK;
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newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL);
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if (!newfunc)
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