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mt76x0: phy: simplify rf configuration routines
Simplify mt76x0_phy_vco_cal and mt76x0_phy_set_chan_rf_params routines using mt76x0_rf_wr, mt76x0_rf_set and mt76x0_rf_clear helper routines. Moreover over get rid of magic numbers Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
9c41078247
commit
d3caa060e1
@ -49,11 +49,11 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
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}
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mt76_wr(dev, MT_RF_CSR_CFG,
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FIELD_PREP(MT_RF_CSR_CFG_DATA, value) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
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MT_RF_CSR_CFG_WR |
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MT_RF_CSR_CFG_KICK);
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FIELD_PREP(MT_RF_CSR_CFG_DATA, value) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
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MT_RF_CSR_CFG_WR |
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MT_RF_CSR_CFG_KICK);
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trace_mt76x0_rf_write(&dev->mt76, bank, offset, value);
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out:
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mutex_unlock(&dev->phy_mutex);
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@ -86,9 +86,9 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
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goto out;
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mt76_wr(dev, MT_RF_CSR_CFG,
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FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
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MT_RF_CSR_CFG_KICK);
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FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
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FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
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MT_RF_CSR_CFG_KICK);
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if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
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goto out;
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@ -168,13 +168,11 @@ mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
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return mt76x0_rf_rmw(dev, offset, 0, val);
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}
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#if 0
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static int
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rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
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mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
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{
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return mt76x0_rf_rmw(dev, offset, mask, 0);
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}
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#endif
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static void
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mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev,
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@ -222,46 +220,31 @@ static void mt76x0_phy_vco_cal(struct mt76x02_dev *dev, u8 channel)
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if ((val & 0x70) != 0x30)
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return;
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/*
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* Calibration Mode - Open loop, closed loop, and amplitude:
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* B0.R06.[0]: 1
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* B0.R06.[3:1] bp_close_code: 100
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* B0.R05.[7:0] bp_open_code: 0x0
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* B0.R04.[2:0] cal_bits: 000
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* B0.R03.[2:0] startup_time: 011
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* B0.R03.[6:4] settle_time:
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* 80MHz channel: 110
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* 40MHz channel: 101
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* 20MHz channel: 100
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*/
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val = mt76x0_rf_rr(dev, MT_RF(0, 6));
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val &= ~0xf;
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val |= 0x09;
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mt76x0_rf_wr(dev, MT_RF(0, 6), val);
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/* closed loop calibarion - B0.R06.[3:0]: 1001 */
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mt76x0_rf_rmw(dev, MT_RF(0, 6), MT_RF_VCO_BP_CLOSE_LOOP_MASK,
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MT_RF_VCO_BP_CLOSE_LOOP | BIT(0));
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val = mt76x0_rf_rr(dev, MT_RF(0, 5));
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if (val != 0)
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mt76x0_rf_wr(dev, MT_RF(0, 5), 0x0);
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/* open loop calibration - B0.R05.[7:0]: 0x0 */
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mt76x0_rf_wr(dev, MT_RF(0, 5), 0x0);
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val = mt76x0_rf_rr(dev, MT_RF(0, 4));
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val &= ~0x07;
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mt76x0_rf_wr(dev, MT_RF(0, 4), val);
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/* caliration mask - B0.R04.[2:0]: 000 */
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mt76x0_rf_clear(dev, MT_RF(0, 4), MT_RF_VCO_CAL_MASK);
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val = mt76x0_rf_rr(dev, MT_RF(0, 3));
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val &= ~0x77;
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if (channel == 1 || channel == 7 || channel == 9 || channel >= 13) {
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val |= 0x63;
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} else if (channel == 3 || channel == 4 || channel == 10) {
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val |= 0x53;
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} else if (channel == 2 || channel == 5 || channel == 6 ||
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channel == 8 || channel == 11 || channel == 12) {
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val |= 0x43;
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} else {
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WARN(1, "Unknown channel %u\n", channel);
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return;
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}
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mt76x0_rf_wr(dev, MT_RF(0, 3), val);
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/* startup time - B0.R03.[2:0] startup_time: 011 */
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mt76x0_rf_rmw(dev, MT_RF(0, 3), MT_RF_START_TIME_MASK,
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MT_RF_START_TIME);
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/* settle_time - B0.R03.[6:4] */
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if (channel == 3 || channel == 4 || channel == 10)
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val = 0x50;
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else if (channel == 2 || channel == 5 || channel == 6 ||
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channel == 8 || channel == 11 || channel == 12)
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val = 0x40;
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else
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val = 0x60;
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mt76x0_rf_rmw(dev, MT_RF(0, 3), MT_RF_SETTLE_TIME_MASK, val);
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/* enable vco */
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mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
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msleep(2);
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@ -297,18 +280,17 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
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static void
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mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band)
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{
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const struct mt76x0_freq_item *freq_item;
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u16 rf_band = rf_bw_band & 0xff00;
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u16 rf_bw = rf_bw_band & 0x00ff;
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enum nl80211_band band;
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bool b_sdm = false;
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u32 mac_reg;
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u8 rf_val;
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int i;
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bool bSDM = false;
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const struct mt76x0_freq_item *freq_item;
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for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) {
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if (channel == mt76x0_sdm_channel[i]) {
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bSDM = true;
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b_sdm = true;
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break;
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}
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}
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@ -317,7 +299,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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if (channel == mt76x0_frequency_plan[i].channel) {
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rf_band = mt76x0_frequency_plan[i].band;
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if (bSDM)
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if (b_sdm)
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freq_item = &(mt76x0_sdm_frequency_plan[i]);
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else
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freq_item = &(mt76x0_frequency_plan[i]);
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@ -328,97 +310,73 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
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mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32));
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rf_val &= ~0xE0;
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rf_val |= freq_item->pllR32_b7b5;
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mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0,
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freq_item->pllR32_b7b5);
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/* R32<4:0> pll_den: (Denomina - 8) */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32));
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rf_val &= ~0x1F;
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rf_val |= freq_item->pllR32_b4b0;
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mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK,
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freq_item->pllR32_b4b0);
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/* R31<7:5> */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31));
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rf_val &= ~0xE0;
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rf_val |= freq_item->pllR31_b7b5;
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mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0,
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freq_item->pllR31_b7b5);
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/* R31<4:0> pll_k(Nominator) */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31));
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rf_val &= ~0x1F;
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rf_val |= freq_item->pllR31_b4b0;
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mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK,
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freq_item->pllR31_b4b0);
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/* R30<7> sdm_reset_n */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x80;
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if (bSDM) {
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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rf_val |= 0x80;
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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if (b_sdm) {
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mt76x0_rf_clear(dev, MT_RF(0, 30),
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MT_RF_SDM_RESET_MASK);
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mt76x0_rf_set(dev, MT_RF(0, 30),
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MT_RF_SDM_RESET_MASK);
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} else {
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rf_val |= freq_item->pllR30_b7;
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 30),
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MT_RF_SDM_RESET_MASK,
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freq_item->pllR30_b7);
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}
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/* R30<6:2> sdmmash_prbs,sin */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x7C;
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rf_val |= freq_item->pllR30_b6b2;
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 30),
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MT_RF_SDM_MASH_PRBS_MASK,
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freq_item->pllR30_b6b2);
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/* R30<1> sdm_bp */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x02;
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rf_val |= (freq_item->pllR30_b1 << 1);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK,
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freq_item->pllR30_b1 << 1);
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/* R30<0> R29<7:0> (hex) pll_n */
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rf_val = freq_item->pll_n & 0x00FF;
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mt76x0_rf_wr(dev, MT_RF(0, 29), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 29),
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freq_item->pll_n & 0xff);
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x1;
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rf_val |= ((freq_item->pll_n >> 8) & 0x0001);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1,
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(freq_item->pll_n >> 8) & 0x1);
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/* R28<7:6> isi_iso */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0xC0;
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rf_val |= freq_item->pllR28_b7b6;
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK,
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freq_item->pllR28_b7b6);
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/* R28<5:4> pfd_dly */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x30;
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rf_val |= freq_item->pllR28_b5b4;
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK,
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freq_item->pllR28_b5b4);
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/* R28<3:2> clksel option */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x0C;
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rf_val |= freq_item->pllR28_b3b2;
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK,
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freq_item->pllR28_b3b2);
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/* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */
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rf_val = freq_item->pll_sdm_k & 0x000000FF;
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mt76x0_rf_wr(dev, MT_RF(0, 26), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 26),
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freq_item->pll_sdm_k & 0xff);
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mt76x0_rf_wr(dev, MT_RF(0, 27),
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(freq_item->pll_sdm_k >> 8) & 0xff);
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rf_val = ((freq_item->pll_sdm_k >> 8) & 0x000000FF);
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mt76x0_rf_wr(dev, MT_RF(0, 27), rf_val);
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x3;
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rf_val |= ((freq_item->pll_sdm_k >> 16) & 0x0003);
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3,
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(freq_item->pll_sdm_k >> 16) & 0x3);
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/* R24<1:0> xo_div */
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 24));
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rf_val &= ~0x3;
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rf_val |= freq_item->pllR24_b1b0;
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mt76x0_rf_wr(dev, MT_RF(0, 24), rf_val);
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mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK,
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freq_item->pllR24_b1b0);
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break;
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}
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@ -445,9 +403,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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}
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}
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mac_reg = mt76_rr(dev, MT_RF_MISC);
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mac_reg &= ~0xC; /* Clear 0x518[3:2] */
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mt76_wr(dev, MT_RF_MISC, mac_reg);
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mt76_clear(dev, MT_RF_MISC, 0xc);
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band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
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if (mt76x02_ext_pa_enabled(dev, band)) {
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@ -456,15 +412,10 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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[2]1'b1: enable external A band PA, 1'b0: disable external A band PA
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[3]1'b1: enable external G band PA, 1'b0: disable external G band PA
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*/
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if (rf_band & RF_A_BAND) {
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mac_reg = mt76_rr(dev, MT_RF_MISC);
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mac_reg |= 0x4;
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mt76_wr(dev, MT_RF_MISC, mac_reg);
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} else {
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mac_reg = mt76_rr(dev, MT_RF_MISC);
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mac_reg |= 0x8;
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mt76_wr(dev, MT_RF_MISC, mac_reg);
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}
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if (rf_band & RF_A_BAND)
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mt76_set(dev, MT_RF_MISC, BIT(2));
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else
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mt76_set(dev, MT_RF_MISC, BIT(3));
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/* External PA */
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for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++)
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@ -710,12 +661,10 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
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mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
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/* set Japan Tx filter at channel 14 */
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val = mt76_rr(dev, MT_BBP(CORE, 1));
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if (channel == 14)
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val |= 0x20;
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mt76_set(dev, MT_BBP(CORE, 1), 0x20);
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else
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val &= ~0x20;
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mt76_wr(dev, MT_BBP(CORE, 1), val);
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mt76_clear(dev, MT_BBP(CORE, 1), 0x20);
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mt76x0_read_rx_gain(dev);
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mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band);
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@ -903,20 +852,16 @@ static void mt76x0_phy_rf_init(struct mt76x02_dev *dev)
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min_t(u8, dev->cal.rx.freq_offset, 0xbf));
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val = mt76x0_rf_rr(dev, MT_RF(0, 22));
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/*
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Reset the DAC (Set B0.R73<7>=1, then set B0.R73<7>=0, and then set B0.R73<7>) during power up.
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/* Reset procedure DAC during power-up:
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* - set B0.R73<7>
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* - clear B0.R73<7>
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* - set B0.R73<7>
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*/
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val = mt76x0_rf_rr(dev, MT_RF(0, 73));
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val |= 0x80;
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mt76x0_rf_wr(dev, MT_RF(0, 73), val);
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val &= ~0x80;
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mt76x0_rf_wr(dev, MT_RF(0, 73), val);
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val |= 0x80;
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
|
||||
mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
|
||||
mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7));
|
||||
mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
|
||||
|
||||
/*
|
||||
vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration.
|
||||
*/
|
||||
/* vcocal_en: initiate VCO calibration (reset after completion)) */
|
||||
mt76x0_rf_set(dev, MT_RF(0, 4), 0x80);
|
||||
}
|
||||
|
||||
|
||||
@ -30,6 +30,23 @@
|
||||
#define MT_RF_BANK(offset) (offset >> 16)
|
||||
#define MT_RF_REG(offset) (offset & 0xff)
|
||||
|
||||
#define MT_RF_VCO_BP_CLOSE_LOOP BIT(3)
|
||||
#define MT_RF_VCO_BP_CLOSE_LOOP_MASK GENMASK(3, 0)
|
||||
#define MT_RF_VCO_CAL_MASK GENMASK(2, 0)
|
||||
#define MT_RF_START_TIME 0x3
|
||||
#define MT_RF_START_TIME_MASK GENMASK(2, 0)
|
||||
#define MT_RF_SETTLE_TIME_MASK GENMASK(6, 4)
|
||||
|
||||
#define MT_RF_PLL_DEN_MASK GENMASK(4, 0)
|
||||
#define MT_RF_PLL_K_MASK GENMASK(4, 0)
|
||||
#define MT_RF_SDM_RESET_MASK BIT(7)
|
||||
#define MT_RF_SDM_MASH_PRBS_MASK GENMASK(6, 2)
|
||||
#define MT_RF_SDM_BP_MASK BIT(1)
|
||||
#define MT_RF_ISI_ISO_MASK GENMASK(7, 6)
|
||||
#define MT_RF_PFD_DLY_MASK GENMASK(5, 4)
|
||||
#define MT_RF_CLK_SEL_MASK GENMASK(3, 2)
|
||||
#define MT_RF_XO_DIV_MASK GENMASK(1, 0)
|
||||
|
||||
struct mt76x0_bbp_switch_item {
|
||||
u16 bw_band;
|
||||
struct mt76_reg_pair reg_pair;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user