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OMAP: DMA: Introduce errata handling feature
Implement errata handling to use flags instead of cpu_is_* and cpu_class_* in the code. The errata flags are initialized at init time and during runtime we are using the errata variable (via the IS_DMA_ERRATA macro) to execute the required errata workaround. Reused errata handling patch from: Peter Ujfalusi <peter.ujfalusi@nokia.com> https://patchwork.kernel.org/patch/231191/ Changes to above patch: 1. Changes are done for converting all the existing errata work arounds to use this feature. 2. Detailed description for each errata is added. 3. Fixed bug in SET_DMA_ERRATA macro 4. Bit shifting in macro definitions are replaced with BIT() macro Signed-off-by: G, Manjunath Kondaiah <manjugk@ti.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
G, Manjunath Kondaiah
Tony Lindgren
parent
a4c537c7f6
commit
d3c9be2f42
@ -144,6 +144,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
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#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
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static int enable_1510_mode;
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static u32 errata;
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static struct omap_dma_global_context_registers {
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u32 dma_irqenable_l0;
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@ -1088,31 +1089,17 @@ void omap_start_dma(int lch)
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cur_lch = next_lch;
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} while (next_lch != -1);
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} else if (cpu_is_omap242x() ||
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(cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
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/* Errata: Need to write lch even if not using chaining */
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} else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
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dma_write(lch, CLNK_CTRL, lch);
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}
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omap_enable_channel_irq(lch);
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l = dma_read(CCR, lch);
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/*
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* Errata: Inter Frame DMA buffering issue (All OMAP2420 and
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* OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
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* bursting is enabled. This might result in data gets stalled in
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* FIFO at the end of the block.
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* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
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* guarantee no data will stay in the DMA FIFO in case inter frame
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* buffering occurs.
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*/
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if (cpu_is_omap2420() ||
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(cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
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l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
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if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
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l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
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l |= OMAP_DMA_CCR_EN;
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dma_write(l, CCR, lch);
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dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
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@ -1128,8 +1115,8 @@ void omap_stop_dma(int lch)
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dma_write(0, CICR, lch);
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l = dma_read(CCR, lch);
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/* OMAP3 Errata i541: sDMA FIFO draining does not finish */
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if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
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if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
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(l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
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int i = 0;
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u32 sys_cf;
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@ -1229,11 +1216,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
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else
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offset = dma_read(CSAC, lch);
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/*
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* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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if (!cpu_is_omap15xx() && offset == 0)
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if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
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offset = dma_read(CSAC, lch);
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if (cpu_class_is_omap1())
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@ -1814,7 +1797,7 @@ int omap_stop_dma_chain_transfers(int chain_id)
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{
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int *channels;
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u32 l, i;
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u32 sys_cf;
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u32 sys_cf = 0;
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/* Check for input params */
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if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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@ -1829,15 +1812,13 @@ int omap_stop_dma_chain_transfers(int chain_id)
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}
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channels = dma_linked_lch[chain_id].linked_dmach_q;
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/*
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* DMA Errata:
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* Special programming model needed to disable DMA before end of block
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*/
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sys_cf = dma_read(OCP_SYSCONFIG, 0);
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l = sys_cf;
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/* Middle mode reg set no Standby */
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l &= ~((1 << 12)|(1 << 13));
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dma_write(l, OCP_SYSCONFIG, 0);
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if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
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sys_cf = dma_read(OCP_SYSCONFIG, 0);
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l = sys_cf;
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/* Middle mode reg set no Standby */
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l &= ~((1 << 12)|(1 << 13));
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dma_write(l, OCP_SYSCONFIG, 0);
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}
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for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
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@ -1856,8 +1837,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
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/* Reset the Queue pointers */
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OMAP_DMA_CHAIN_QINIT(chain_id);
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/* Errata - put in the old value */
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dma_write(sys_cf, OCP_SYSCONFIG, 0);
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if (IS_DMA_ERRATA(DMA_ERRATA_i88))
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dma_write(sys_cf, OCP_SYSCONFIG, 0);
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return 0;
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}
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@ -2063,12 +2044,7 @@ static int omap2_dma_handle_ch(int ch)
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if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
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printk(KERN_INFO "DMA transaction error with device %d\n",
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dma_chan[ch].dev_id);
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if (cpu_class_is_omap2()) {
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/*
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* Errata: sDMA Channel is not disabled
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* after a transaction error. So we explicitely
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* disable the channel
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*/
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if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
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u32 ccr;
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ccr = dma_read(CCR, ch);
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@ -2168,13 +2144,7 @@ void omap_dma_global_context_restore(void)
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dma_write(omap_dma_global_context.dma_irqenable_l0,
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IRQENABLE_L0, 0);
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/*
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* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
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* after secure sram context save and restore. Hence we need to
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* manually clear those IRQs to avoid spurious interrupts. This
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* affects only secure devices.
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*/
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if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
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dma_write(0x3 , IRQSTATUS_L0, 0);
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for (ch = 0; ch < dma_chan_count; ch++)
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@ -2182,6 +2152,87 @@ void omap_dma_global_context_restore(void)
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omap_clear_dma(ch);
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}
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static void configure_dma_errata(void)
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{
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/*
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* Errata applicable for OMAP2430ES1.0 and all omap2420
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*
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* I.
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* Erratum ID: Not Available
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* Inter Frame DMA buffering issue DMA will wrongly
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* buffer elements if packing and bursting is enabled. This might
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* result in data gets stalled in FIFO at the end of the block.
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* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
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* guarantee no data will stay in the DMA FIFO in case inter frame
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* buffering occurs
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*
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* II.
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* Erratum ID: Not Available
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* DMA may hang when several channels are used in parallel
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* In the following configuration, DMA channel hanging can occur:
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* a. Channel i, hardware synchronized, is enabled
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* b. Another channel (Channel x), software synchronized, is enabled.
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* c. Channel i is disabled before end of transfer
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* d. Channel i is reenabled.
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* e. Steps 1 to 4 are repeated a certain number of times.
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* f. A third channel (Channel y), software synchronized, is enabled.
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* Channel x and Channel y may hang immediately after step 'f'.
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* Workaround:
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* For any channel used - make sure NextLCH_ID is set to the value j.
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*/
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if (cpu_is_omap2420() || (cpu_is_omap2430() &&
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(omap_type() == OMAP2430_REV_ES1_0))) {
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SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
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SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
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}
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/*
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* Erratum ID: i378: OMAP2plus: sDMA Channel is not disabled
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* after a transaction error.
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* Workaround: SW should explicitely disable the channel.
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*/
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if (cpu_class_is_omap2())
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SET_DMA_ERRATA(DMA_ERRATA_i378);
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/*
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* Erratum ID: i541: sDMA FIFO draining does not finish
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* If sDMA channel is disabled on the fly, sDMA enters standby even
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* through FIFO Drain is still in progress
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* Workaround: Put sDMA in NoStandby more before a logical channel is
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* disabled, then put it back to SmartStandby right after the channel
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* finishes FIFO draining.
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*/
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if (cpu_is_omap34xx())
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SET_DMA_ERRATA(DMA_ERRATA_i541);
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/*
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* Erratum ID: i88 : Special programming model needed to disable DMA
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* before end of block.
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* Workaround: software must ensure that the DMA is configured in No
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* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
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*/
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if (cpu_is_omap34xx() && (omap_type() == OMAP3430_REV_ES1_0))
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SET_DMA_ERRATA(DMA_ERRATA_i88);
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/*
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* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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if (!cpu_is_omap15xx())
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SET_DMA_ERRATA(DMA_ERRATA_3_3);
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/*
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* Erratum ID: Not Available
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* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
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* after secure sram context save and restore.
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* Work around: Hence we need to manually clear those IRQs to avoid
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* spurious interrupts. This affects only secure devices.
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*/
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if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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SET_DMA_ERRATA(DMA_ROMCODE_BUG);
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}
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/*----------------------------------------------------------------------------*/
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static int __init omap_init_dma(void)
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@ -2342,6 +2393,7 @@ static int __init omap_init_dma(void)
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dma_chan[1].dev_id = 1;
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}
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}
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configure_dma_errata();
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return 0;
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@ -283,6 +283,18 @@
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#define DMA_CH_PRIO_HIGH 0x1
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#define DMA_CH_PRIO_LOW 0x0 /* Def */
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/* Errata handling */
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#define IS_DMA_ERRATA(id) (errata & (id))
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#define SET_DMA_ERRATA(id) (errata |= (id))
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#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
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#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
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#define DMA_ERRATA_i378 BIT(0x2)
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#define DMA_ERRATA_i541 BIT(0x3)
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#define DMA_ERRATA_i88 BIT(0x4)
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#define DMA_ERRATA_3_3 BIT(0x5)
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#define DMA_ROMCODE_BUG BIT(0x6)
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enum omap_reg_offsets {
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GCR, GSCR, GRST1, HW_ID,
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