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ARM: omap1: move 32k counter from plat-omap to mach-omap1
omap2 stopped using this code with commit 8d39ff3d16 ("ARM: OMAP2+:
Remove unused legacy code for timer"), so just move it to mach-omap1 now,
along with the other half of that driver.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
9fe1531656
commit
d379e8899a
@ -53,6 +53,22 @@ config OMAP_MUX_WARNINGS
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to change the pin multiplexing setup. When there are no warnings
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printed, it's safe to deselect OMAP_MUX for your product.
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config OMAP_32K_TIMER
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bool "Use 32KHz timer"
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depends on ARCH_OMAP16XX
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default ARCH_OMAP16XX
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help
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Select this option if you want to enable the OMAP 32KHz timer.
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This timer saves power compared to the OMAP_MPU_TIMER, and has
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support for no tick during idle. The 32KHz timer provides less
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intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
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currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
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On OMAP2PLUS this value is only used for CONFIG_HZ and
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CLOCK_TICK_RATE compile time calculation.
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The actual timer selection is done in the board file
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through the (DT_)MACHINE_START structure.
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comment "OMAP Board Type"
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config MACH_OMAP_INNOVATOR
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@ -45,15 +45,13 @@
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/sched_clock.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <plat/counter-32k.h>
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#include <mach/hardware.h>
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#include "common.h"
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/*
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@ -159,6 +157,98 @@ static __init void omap_init_32k_timer(void)
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OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
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}
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/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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static void __iomem *sync32k_cnt_reg;
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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}
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/**
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* omap_read_persistent_clock64 - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec64.
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*/
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static struct timespec64 persistent_ts;
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static cycles_t cycles;
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static unsigned int persistent_mult, persistent_shift;
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static void omap_read_persistent_clock64(struct timespec64 *ts)
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{
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unsigned long long nsecs;
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cycles_t last_cycles;
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last_cycles = cycles;
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cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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nsecs = clocksource_cyc2ns(cycles - last_cycles,
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persistent_mult, persistent_shift);
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timespec64_add_ns(&persistent_ts, nsecs);
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*ts = persistent_ts;
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}
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/**
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* omap_init_clocksource_32k - setup and register counter 32k as a
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* kernel clocksource
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* @pbase: base addr of counter_32k module
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* @size: size of counter_32k to map
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*
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* Returns 0 upon success or negative error code upon failure.
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*
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*/
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int __init omap_init_clocksource_32k(void __iomem *vbase)
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{
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int ret;
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/*
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* 32k sync Counter IP register offsets vary between the
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* highlander version and the legacy ones.
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* The 'SCHEME' bits(30-31) of the revision register is used
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* to identify the version.
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*/
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if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_update_freq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
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250, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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register_persistent_clock(omap_read_persistent_clock64);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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@ -72,23 +72,6 @@ config OMAP_MPU_TIMER
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timer provides more intra-tick resolution than the 32KHz timer,
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but consumes more power.
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config OMAP_32K_TIMER
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bool "Use 32KHz timer"
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depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
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default y if (ARCH_OMAP16XX || ARCH_OMAP2PLUS)
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help
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Select this option if you want to enable the OMAP 32KHz timer.
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This timer saves power compared to the OMAP_MPU_TIMER, and has
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support for no tick during idle. The 32KHz timer provides less
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intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
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currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
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On OMAP2PLUS this value is only used for CONFIG_HZ and
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CLOCK_TICK_RATE compile time calculation.
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The actual timer selection is done in the board file
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through the (DT_)MACHINE_START structure.
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config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
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bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
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depends on ARCH_OMAP3 && PM
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@ -6,7 +6,7 @@
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
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# Common support
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obj-y := sram.o dma.o counter_32k.o
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obj-y := sram.o dma.o
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# omap_device support (OMAP2+ only at the moment)
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@ -1,114 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP 32ksynctimer/counter_32k-related code
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*
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* Copyright (C) 2009 Texas Instruments
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* Copyright (C) 2010 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#include <plat/counter-32k.h>
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/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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static void __iomem *sync32k_cnt_reg;
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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}
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/**
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* omap_read_persistent_clock64 - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec64.
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*/
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static struct timespec64 persistent_ts;
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static cycles_t cycles;
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static unsigned int persistent_mult, persistent_shift;
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static void omap_read_persistent_clock64(struct timespec64 *ts)
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{
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unsigned long long nsecs;
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cycles_t last_cycles;
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last_cycles = cycles;
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cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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nsecs = clocksource_cyc2ns(cycles - last_cycles,
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persistent_mult, persistent_shift);
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timespec64_add_ns(&persistent_ts, nsecs);
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*ts = persistent_ts;
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}
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/**
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* omap_init_clocksource_32k - setup and register counter 32k as a
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* kernel clocksource
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* @pbase: base addr of counter_32k module
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* @size: size of counter_32k to map
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*
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* Returns 0 upon success or negative error code upon failure.
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*
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*/
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int __init omap_init_clocksource_32k(void __iomem *vbase)
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{
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int ret;
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/*
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* 32k sync Counter IP register offsets vary between the
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* highlander version and the legacy ones.
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* The 'SCHEME' bits(30-31) of the revision register is used
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* to identify the version.
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*/
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if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_update_freq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
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250, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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register_persistent_clock(omap_read_persistent_clock64);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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@ -1 +0,0 @@
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int omap_init_clocksource_32k(void __iomem *vbase);
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