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[TG3]: Add 5784 and 5764 support.
This patch adds the support for 5784 and 5764 devices. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
795d01c523
commit
d30cdd28fb
@ -198,6 +198,8 @@ static struct pci_device_id tg3_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
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{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
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{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
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{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
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@ -4921,7 +4923,8 @@ static int tg3_chip_reset(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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tw32(GRC_FASTBOOT_PC, 0);
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/*
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@ -6146,6 +6149,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tg3_write_sig_legacy(tp, RESET_KIND_INIT);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
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val = tr32(TG3_CPMU_CTRL);
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val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
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tw32(TG3_CPMU_CTRL, val);
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}
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/* This works around an issue with Athlon chipsets on
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* B3 tigon3 silicon. This bit has no effect on any
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* other revision. But do not set this on PCI Express
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@ -6180,10 +6189,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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if (err)
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return err;
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/* This value is determined during the probe time DMA
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* engine test, tg3_test_dma.
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*/
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) {
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/* This value is determined during the probe time DMA
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* engine test, tg3_test_dma.
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*/
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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}
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tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
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GRC_MODE_4X_NIC_SEND_RINGS |
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@ -6417,6 +6428,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
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RDMAC_MODE_LNGREAD_ENAB);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
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RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
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RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
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/* If statement applies to 5705 and 5750 PCI devices only */
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
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tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
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@ -6578,7 +6594,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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/* Enable host coalescing bug fix */
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
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val |= (1 << 29);
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tw32_f(WDMAC_MODE, val);
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@ -8353,7 +8370,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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ethtool_op_set_tx_ipv6_csum(dev, data);
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else
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ethtool_op_set_tx_csum(dev, data);
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@ -8849,7 +8867,8 @@ static int tg3_test_memory(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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mem_tbl = mem_tbl_5755;
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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mem_tbl = mem_tbl_5906;
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@ -9600,7 +9619,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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tg3_get_5752_nvram_info(tp);
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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tg3_get_5755_nvram_info(tp);
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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tg3_get_5787_nvram_info(tp);
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tg3_get_5906_nvram_info(tp);
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@ -9913,6 +9933,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
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(tp->nvram_jedecnum == JEDEC_ST) &&
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(nvram_cmd & NVRAM_CMD_FIRST)) {
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@ -10657,6 +10678,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
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@ -10676,6 +10698,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
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@ -10693,6 +10716,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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@ -10868,6 +10892,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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*/
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tg3_get_eeprom_hw_cfg(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
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/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
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* GPIO1 driven high will bring 5700's external PHY out of reset.
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* It is also used as eeprom write protect on LOMs.
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@ -10934,7 +10961,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) {
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if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
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tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
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tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
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@ -11077,6 +11105,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tp->dev->hard_start_xmit = tg3_start_xmit;
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else
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@ -11698,6 +11727,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
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case PHY_ID_BCM5780: return "5780";
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case PHY_ID_BCM5755: return "5755";
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case PHY_ID_BCM5787: return "5787";
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case PHY_ID_BCM5784: return "5784";
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case PHY_ID_BCM5756: return "5722/5756";
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case PHY_ID_BCM5906: return "5906";
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case PHY_ID_BCM8002: return "8002/serdes";
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@ -12042,7 +12072,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
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dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
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dev->features |= NETIF_F_IPV6_CSUM;
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tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
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@ -108,6 +108,7 @@
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#define CHIPREV_ID_5752_A1 0x6001
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#define CHIPREV_ID_5714_A2 0x9002
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#define CHIPREV_ID_5906_A1 0xc001
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#define CHIPREV_ID_5784_A0 0x5784000
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#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
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#define ASIC_REV_5700 0x07
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#define ASIC_REV_5701 0x00
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@ -122,6 +123,7 @@
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#define ASIC_REV_5787 0x0b
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#define ASIC_REV_5906 0x0c
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#define ASIC_REV_USE_PROD_ID_REG 0x0f
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#define ASIC_REV_5784 0x5784
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#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
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#define CHIPREV_5700_AX 0x70
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#define CHIPREV_5700_BX 0x71
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@ -843,7 +845,13 @@
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#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
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#define RCVLSC_STATUS 0x00003404
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#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
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/* 0x3408 --> 0x3800 unused */
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/* 0x3408 --> 0x3600 unused */
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/* CPMU registers */
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#define TG3_CPMU_CTRL 0x00003600
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#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
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#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
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/* 0x3604 --> 0x3800 unused */
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/* Mbuf cluster free registers */
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#define MBFREE_MODE 0x00003800
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@ -1023,7 +1031,10 @@
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#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
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#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
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#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
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#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
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#define RDMAC_MODE_SPLIT_RESET 0x00001000
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#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
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#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
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#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
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#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
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#define RDMAC_STATUS 0x00004804
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@ -2315,6 +2326,7 @@ struct tg3 {
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#define PHY_ID_BCM5755 0xbc050cc0
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM5756 0xbc050ed0
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#define PHY_ID_BCM5784 0xbc050fa0
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#define PHY_ID_BCM5906 0xdc00ac40
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#define PHY_ID_BCM8002 0x60010140
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#define PHY_ID_INVALID 0xffffffff
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@ -1950,8 +1950,10 @@
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#define PCI_DEVICE_ID_TIGON3_5751M 0x167d
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#define PCI_DEVICE_ID_TIGON3_5751F 0x167e
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#define PCI_DEVICE_ID_TIGON3_5787F 0x167f
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#define PCI_DEVICE_ID_TIGON3_5764 0x1684
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#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
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#define PCI_DEVICE_ID_TIGON3_5782 0x1696
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#define PCI_DEVICE_ID_TIGON3_5784 0x1698
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#define PCI_DEVICE_ID_TIGON3_5786 0x169a
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#define PCI_DEVICE_ID_TIGON3_5787 0x169b
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#define PCI_DEVICE_ID_TIGON3_5788 0x169c
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