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pinctrl: rockchip: Add rk3128 pinctrl support
There are 3 IP blocks pin routes need to be switched, that are emmc-cmd, spi, i2s. And there are some pins need to be recalced, which are gpio2c4~gpio2c7 and gpio2d0. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
David Wu
Linus Walleij
parent
c04c3fa65a
commit
d23c66df1a
@ -24,6 +24,7 @@ Required properties for iomux controller:
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"rockchip,rk2928-pinctrl": for Rockchip RK2928
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"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
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"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
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"rockchip,rk3128-pinctrl": for Rockchip RK3128
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"rockchip,rk3188-pinctrl": for Rockchip RK3188
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"rockchip,rk3228-pinctrl": for Rockchip RK3228
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"rockchip,rk3288-pinctrl": for Rockchip RK3288
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@ -62,6 +62,7 @@ enum rockchip_pinctrl_type {
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RV1108,
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RK2928,
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RK3066B,
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RK3128,
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RK3188,
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RK3288,
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RK3368,
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@ -557,6 +558,40 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
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* Hardware access
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*/
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static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
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{
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.num = 2,
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.pin = 20,
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.reg = 0xe8,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 21,
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.reg = 0xe8,
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.bit = 4,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 22,
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.reg = 0xe8,
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.bit = 8,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 23,
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.reg = 0xe8,
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.bit = 12,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 24,
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.reg = 0xd4,
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.bit = 12,
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.mask = 0x7
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},
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};
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static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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{
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.num = 2,
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@ -602,6 +637,59 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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*bit = data->bit;
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}
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static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
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{
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/* spi-0 */
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.bank_num = 1,
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.pin = 10,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4),
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}, {
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/* spi-1 */
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.bank_num = 1,
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.pin = 27,
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.func = 3,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
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}, {
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/* spi-2 */
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.bank_num = 0,
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.pin = 13,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
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}, {
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/* i2s-0 */
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.bank_num = 1,
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.pin = 5,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 5),
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}, {
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/* i2s-1 */
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.bank_num = 0,
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.pin = 14,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 5) | BIT(5),
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}, {
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/* emmc-0 */
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.bank_num = 1,
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.pin = 22,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 6),
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}, {
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/* emmc-1 */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 6) | BIT(6),
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},
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};
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static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
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{
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/* pwm0-0 */
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@ -1102,6 +1190,22 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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*bit = pin_num % RK2928_PULL_PINS_PER_REG;
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};
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#define RK3128_PULL_OFFSET 0x118
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static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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*regmap = info->regmap_base;
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*reg = RK3128_PULL_OFFSET;
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*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
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*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK2928_PULL_PINS_PER_REG;
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}
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#define RK3188_PULL_OFFSET 0x164
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#define RK3188_PULL_BITS_PER_PIN 2
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#define RK3188_PULL_PINS_PER_REG 8
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@ -1571,6 +1675,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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switch (ctrl->type) {
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case RK2928:
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case RK3128:
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return !(data & BIT(bit))
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? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
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: PIN_CONFIG_BIAS_DISABLE;
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@ -1611,6 +1716,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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switch (ctrl->type) {
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case RK2928:
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case RK3128:
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data = BIT(bit + 16);
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if (pull == PIN_CONFIG_BIAS_DISABLE)
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data |= BIT(bit);
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@ -1865,6 +1971,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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{
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switch (ctrl->type) {
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case RK2928:
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case RK3128:
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return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
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pull == PIN_CONFIG_BIAS_DISABLE);
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case RK3066B:
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@ -3093,6 +3200,26 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
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.grf_mux_offset = 0x60,
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};
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static struct rockchip_pin_bank rk3128_pin_banks[] = {
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PIN_BANK(0, 32, "gpio0"),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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PIN_BANK(3, 32, "gpio3"),
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};
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static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
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.pin_banks = rk3128_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
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.label = "RK3128-GPIO",
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.type = RK3128,
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.grf_mux_offset = 0xa8,
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.iomux_recalced = rk3128_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
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.iomux_routes = rk3128_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
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.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
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};
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static struct rockchip_pin_bank rk3188_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
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PIN_BANK(1, 32, "gpio1"),
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@ -3301,6 +3428,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
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.data = &rk3066a_pin_ctrl },
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{ .compatible = "rockchip,rk3066b-pinctrl",
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.data = &rk3066b_pin_ctrl },
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{ .compatible = "rockchip,rk3128-pinctrl",
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.data = (void *)&rk3128_pin_ctrl },
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{ .compatible = "rockchip,rk3188-pinctrl",
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.data = &rk3188_pin_ctrl },
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{ .compatible = "rockchip,rk3228-pinctrl",
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