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Merge branch 'pci/host-tegra' into next
* pci/host-tegra: PCI: tegra: Add Tegra186 PCIe support dt-bindings: pci: tegra: Document Tegra186 PCIe DT PCI: tegra: Use generic accessors where possible
This commit is contained in:
Bjorn Helgaas
commit
d238be6957
@ -1,10 +1,15 @@
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NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
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"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
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Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
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<chip> is tegra132 or tegra210.
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- compatible: Must be:
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- "nvidia,tegra20-pcie": for Tegra20
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- "nvidia,tegra30-pcie": for Tegra30
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- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
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- "nvidia,tegra210-pcie": for Tegra210
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- "nvidia,tegra186-pcie": for Tegra186
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- power-domains: To ungate power partition by BPMP powergate driver. Must
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contain BPMP phandle and PCIe power partition ID. This is required only
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for Tegra186.
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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@ -124,6 +129,16 @@ Power supplies for Tegra210:
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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Power supplies for Tegra186:
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- Required:
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- dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
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supply 1.8 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 1.8 V.
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- vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
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supply 1.8 V.
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Root ports are defined as subnodes of the PCIe controller node.
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Required properties:
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@ -546,3 +561,114 @@ Board DTS:
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status = "okay";
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};
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};
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Tegra186:
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---------
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SoC DTSI:
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pcie@10003000 {
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compatible = "nvidia,tegra186-pcie";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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0x0 0x10003800 0x0 0x00000800 /* AFI registers */
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0x0 0x40000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
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0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
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clocks = <&bpmp TEGRA186_CLK_AFI>,
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<&bpmp TEGRA186_CLK_PCIE>,
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<&bpmp TEGRA186_CLK_PLLE>;
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clock-names = "afi", "pex", "pll_e";
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resets = <&bpmp TEGRA186_RESET_AFI>,
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<&bpmp TEGRA186_RESET_PCIE>,
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<&bpmp TEGRA186_RESET_PCIEXCLK>;
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reset-names = "afi", "pex", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie@10003000 {
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status = "okay";
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dvdd-pex-supply = <&vdd_pex>;
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hvdd-pex-pll-supply = <&vdd_1v8>;
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hvdd-pex-supply = <&vdd_1v8>;
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vddio-pexctl-aud-supply = <&vdd_1v8>;
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pci@1,0 {
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nvidia,num-lanes = <4>;
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status = "okay";
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};
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pci@2,0 {
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nvidia,num-lanes = <0>;
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status = "disabled";
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};
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pci@3,0 {
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nvidia,num-lanes = <1>;
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status = "disabled";
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};
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};
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@ -159,10 +159,13 @@
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111 (0x2 << 20)
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#define AFI_FUSE 0x104
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#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
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@ -252,6 +255,7 @@ struct tegra_pcie_soc {
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bool has_cml_clk;
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bool has_gen2;
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bool force_pca_enable;
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bool program_uphy;
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};
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static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
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@ -491,12 +495,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
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return addr;
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}
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static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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if (bus->number == 0)
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return pci_generic_config_read32(bus, devfn, where, size,
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value);
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return pci_generic_config_read(bus, devfn, where, size, value);
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}
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static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (bus->number == 0)
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return pci_generic_config_write32(bus, devfn, where, size,
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value);
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return pci_generic_config_write(bus, devfn, where, size, value);
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}
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static struct pci_ops tegra_pcie_ops = {
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.add_bus = tegra_pcie_add_bus,
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.remove_bus = tegra_pcie_remove_bus,
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.map_bus = tegra_pcie_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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.read = tegra_pcie_config_read,
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.write = tegra_pcie_config_write,
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};
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static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
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@ -1012,10 +1036,12 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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afi_writel(pcie, value, AFI_FUSE);
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}
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err = tegra_pcie_phy_power_on(pcie);
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if (err < 0) {
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dev_err(dev, "failed to power on PHY(s): %d\n", err);
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return err;
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if (soc->program_uphy) {
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err = tegra_pcie_phy_power_on(pcie);
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if (err < 0) {
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dev_err(dev, "failed to power on PHY(s): %d\n", err);
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return err;
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}
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}
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/* take the PCIe interface module out of reset */
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@ -1048,19 +1074,23 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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const struct tegra_pcie_soc *soc = pcie->soc;
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int err;
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/* TODO: disable and unprepare clocks? */
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err = tegra_pcie_phy_power_off(pcie);
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if (err < 0)
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dev_err(dev, "failed to power off PHY(s): %d\n", err);
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if (soc->program_uphy) {
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err = tegra_pcie_phy_power_off(pcie);
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if (err < 0)
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dev_err(dev, "failed to power off PHY(s): %d\n", err);
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}
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reset_control_assert(pcie->pcie_xrst);
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reset_control_assert(pcie->afi_rst);
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reset_control_assert(pcie->pex_rst);
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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if (!dev->pm_domain)
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
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if (err < 0)
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@ -1077,19 +1107,29 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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reset_control_assert(pcie->afi_rst);
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reset_control_assert(pcie->pex_rst);
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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if (!dev->pm_domain)
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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/* enable regulators */
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err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
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if (err < 0)
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dev_err(dev, "failed to enable regulators: %d\n", err);
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
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pcie->pex_clk,
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pcie->pex_rst);
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if (err) {
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dev_err(dev, "powerup sequence failed: %d\n", err);
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return err;
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if (dev->pm_domain) {
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err = clk_prepare_enable(pcie->pex_clk);
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if (err) {
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dev_err(dev, "failed to enable PEX clock: %d\n", err);
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return err;
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}
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reset_control_deassert(pcie->pex_rst);
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} else {
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
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pcie->pex_clk,
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pcie->pex_rst);
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if (err) {
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dev_err(dev, "powerup sequence failed: %d\n", err);
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return err;
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}
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}
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reset_control_deassert(pcie->afi_rst);
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@ -1262,6 +1302,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *pads, *afi, *res;
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const struct tegra_pcie_soc *soc = pcie->soc;
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int err;
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err = tegra_pcie_clocks_get(pcie);
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@ -1276,10 +1317,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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return err;
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}
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err = tegra_pcie_phys_get(pcie);
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if (err < 0) {
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dev_err(dev, "failed to get PHYs: %d\n", err);
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return err;
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if (soc->program_uphy) {
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err = tegra_pcie_phys_get(pcie);
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if (err < 0) {
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dev_err(dev, "failed to get PHYs: %d\n", err);
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return err;
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}
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}
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err = tegra_pcie_power_on(pcie);
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@ -1341,6 +1384,7 @@ poweroff:
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static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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const struct tegra_pcie_soc *soc = pcie->soc;
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int err;
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if (pcie->irq > 0)
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@ -1348,9 +1392,11 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
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tegra_pcie_power_off(pcie);
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err = phy_exit(pcie->phy);
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if (err < 0)
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dev_err(dev, "failed to teardown PHY: %d\n", err);
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if (soc->program_uphy) {
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err = phy_exit(pcie->phy);
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if (err < 0)
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dev_err(dev, "failed to teardown PHY: %d\n", err);
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}
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return 0;
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}
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@ -1616,8 +1662,32 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
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struct device *dev = pcie->dev;
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struct device_node *np = dev->of_node;
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if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
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of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
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if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
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switch (lanes) {
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case 0x010004:
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dev_info(dev, "4x1, 1x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401;
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return 0;
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case 0x010102:
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dev_info(dev, "2x1, 1X1, 1x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
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return 0;
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case 0x010101:
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dev_info(dev, "1x1, 1x1, 1x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111;
|
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return 0;
|
||||
|
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default:
|
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dev_info(dev, "wrong configuration updated in DT, "
|
||||
"switching to default 2x1, 1x1, 1x1 "
|
||||
"configuration\n");
|
||||
*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
|
||||
return 0;
|
||||
}
|
||||
} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
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of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
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switch (lanes) {
|
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case 0x0000104:
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dev_info(dev, "4x1, 1x1 configuration\n");
|
||||
@ -1737,7 +1807,20 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
|
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struct device_node *np = dev->of_node;
|
||||
unsigned int i = 0;
|
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|
||||
if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
|
||||
if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
|
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pcie->num_supplies = 4;
|
||||
|
||||
pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
|
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sizeof(*pcie->supplies),
|
||||
GFP_KERNEL);
|
||||
if (!pcie->supplies)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->supplies[i++].supply = "dvdd-pex";
|
||||
pcie->supplies[i++].supply = "hvdd-pex-pll";
|
||||
pcie->supplies[i++].supply = "hvdd-pex";
|
||||
pcie->supplies[i++].supply = "vddio-pexctl-aud";
|
||||
} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
|
||||
pcie->num_supplies = 6;
|
||||
|
||||
pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
|
||||
@ -2076,6 +2159,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
|
||||
.has_cml_clk = false,
|
||||
.has_gen2 = false,
|
||||
.force_pca_enable = false,
|
||||
.program_uphy = true,
|
||||
};
|
||||
|
||||
static const struct tegra_pcie_soc tegra30_pcie = {
|
||||
@ -2091,6 +2175,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
|
||||
.has_cml_clk = true,
|
||||
.has_gen2 = false,
|
||||
.force_pca_enable = false,
|
||||
.program_uphy = true,
|
||||
};
|
||||
|
||||
static const struct tegra_pcie_soc tegra124_pcie = {
|
||||
@ -2105,6 +2190,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
|
||||
.has_cml_clk = true,
|
||||
.has_gen2 = true,
|
||||
.force_pca_enable = false,
|
||||
.program_uphy = true,
|
||||
};
|
||||
|
||||
static const struct tegra_pcie_soc tegra210_pcie = {
|
||||
@ -2119,9 +2205,27 @@ static const struct tegra_pcie_soc tegra210_pcie = {
|
||||
.has_cml_clk = true,
|
||||
.has_gen2 = true,
|
||||
.force_pca_enable = true,
|
||||
.program_uphy = true,
|
||||
};
|
||||
|
||||
static const struct tegra_pcie_soc tegra186_pcie = {
|
||||
.num_ports = 3,
|
||||
.msi_base_shift = 8,
|
||||
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
|
||||
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
|
||||
.pads_refclk_cfg0 = 0x80b880b8,
|
||||
.pads_refclk_cfg1 = 0x000480b8,
|
||||
.has_pex_clkreq_en = true,
|
||||
.has_pex_bias_ctrl = true,
|
||||
.has_intr_prsnt_sense = true,
|
||||
.has_cml_clk = false,
|
||||
.has_gen2 = true,
|
||||
.force_pca_enable = false,
|
||||
.program_uphy = false,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_pcie_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
|
||||
{ .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
|
||||
{ .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
|
||||
{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user