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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2021-02-02 14:21:31 -08:00
commit d1e1355aef
188 changed files with 2058 additions and 780 deletions
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11
.clang-format
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@ -122,6 +122,7 @@ ForEachMacros:
- 'drm_for_each_bridge_in_chain'
- 'drm_for_each_connector_iter'
- 'drm_for_each_crtc'
- 'drm_for_each_crtc_reverse'
- 'drm_for_each_encoder'
- 'drm_for_each_encoder_mask'
- 'drm_for_each_fb'
@ -203,14 +204,13 @@ ForEachMacros:
- 'for_each_matching_node'
- 'for_each_matching_node_and_match'
- 'for_each_member'
- 'for_each_mem_region'
- 'for_each_memblock_type'
- 'for_each_memcg_cache_index'
- 'for_each_mem_pfn_range'
- '__for_each_mem_range'
- 'for_each_mem_range'
- '__for_each_mem_range_rev'
- 'for_each_mem_range_rev'
- 'for_each_mem_region'
- 'for_each_migratetype_order'
- 'for_each_msi_entry'
- 'for_each_msi_entry_safe'
@ -276,10 +276,8 @@ ForEachMacros:
- 'for_each_reserved_mem_range'
- 'for_each_reserved_mem_region'
- 'for_each_rtd_codec_dais'
- 'for_each_rtd_codec_dais_rollback'
- 'for_each_rtd_components'
- 'for_each_rtd_cpu_dais'
- 'for_each_rtd_cpu_dais_rollback'
- 'for_each_rtd_dais'
- 'for_each_set_bit'
- 'for_each_set_bit_from'
@ -298,6 +296,7 @@ ForEachMacros:
- '__for_each_thread'
- 'for_each_thread'
- 'for_each_unicast_dest_pgid'
- 'for_each_vsi'
- 'for_each_wakeup_source'
- 'for_each_zone'
- 'for_each_zone_zonelist'
@ -330,6 +329,7 @@ ForEachMacros:
- 'hlist_for_each_entry_rcu_bh'
- 'hlist_for_each_entry_rcu_notrace'
- 'hlist_for_each_entry_safe'
- 'hlist_for_each_entry_srcu'
- '__hlist_for_each_rcu'
- 'hlist_for_each_safe'
- 'hlist_nulls_for_each_entry'
@ -378,6 +378,7 @@ ForEachMacros:
- 'list_for_each_entry_safe_continue'
- 'list_for_each_entry_safe_from'
- 'list_for_each_entry_safe_reverse'
- 'list_for_each_entry_srcu'
- 'list_for_each_prev'
- 'list_for_each_prev_safe'
- 'list_for_each_safe'
@ -411,6 +412,8 @@ ForEachMacros:
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'
- 'ping_portaddr_for_each_entry'
- 'plist_for_each'

16
Documentation/admin-guide/media/rkisp1.rst
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@ -13,6 +13,22 @@ This file documents the driver for the Rockchip ISP1 that is part of RK3288
and RK3399 SoCs. The driver is located under drivers/staging/media/rkisp1
and uses the Media-Controller API.
Revisions
=========
There exist multiple smaller revisions to this ISP that got introduced in
later SoCs. Revisions can be found in the enum :c:type:`rkisp1_cif_isp_version`
in the UAPI and the revision of the ISP inside the running SoC can be read
in the field hw_revision of struct media_device_info as returned by
ioctl MEDIA_IOC_DEVICE_INFO.
Versions in use are:
- RKISP1_V10: used at least in rk3288 and rk3399
- RKISP1_V11: declared in the original vendor code, but not used
- RKISP1_V12: used at least in rk3326 and px30
- RKISP1_V13: used at least in rk1808
Topology
========
.. _rkisp1_topology_graph:

5
Documentation/asm-annotations.rst
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@ -100,6 +100,11 @@ Instruction Macros
~~~~~~~~~~~~~~~~~~
This section covers ``SYM_FUNC_*`` and ``SYM_CODE_*`` enumerated above.
``objtool`` requires that all code must be contained in an ELF symbol. Symbol
names that have a ``.L`` prefix do not emit symbol table entries. ``.L``
prefixed symbols can be used within a code region, but should be avoided for
denoting a range of code via ``SYM_*_START/END`` annotations.
* ``SYM_FUNC_START`` and ``SYM_FUNC_START_LOCAL`` are supposed to be **the
most frequent markings**. They are used for functions with standard calling
conventions -- global and local. Like in C, they both align the functions to

1
Documentation/devicetree/bindings/arm/cpus.yaml
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@ -232,7 +232,6 @@ properties:
by this cpu (see ./idle-states.yaml).
capacity-dmips-mhz:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
u32 value representing CPU capacity (see ./cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz

2
Documentation/devicetree/bindings/display/bridge/sii902x.txt
View File

@ -40,7 +40,7 @@ Optional properties:
documents on how to describe the way the sii902x device is
connected to the rest of the audio system:
Documentation/devicetree/bindings/sound/simple-card.yaml
Documentation/devicetree/bindings/sound/audio-graph-card.txt
Documentation/devicetree/bindings/sound/audio-graph-card.yaml
Note: In case of the audio-graph-card binding the used port
index should be 3.

4
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
View File

@ -23,7 +23,7 @@ connected to.
For a description of the display interface sink function blocks, see
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
Required properties (all function blocks):
- compatible: "mediatek,<chip>-disp-<function>", one of
@ -61,7 +61,7 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-wdma"
the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
- iommus: Should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.

1
Documentation/devicetree/bindings/extcon/wlf,arizona.yaml
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@ -85,7 +85,6 @@ properties:
wlf,micd-timeout-ms:
description:
Timeout for microphone detection, specified in milliseconds.
$ref: "/schemas/types.yaml#/definitions/uint32"
wlf,micd-force-micbias:
description:

1
Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml
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@ -49,7 +49,6 @@ properties:
description:
This property controls the Accumulation Dead band which allows to set the
level of current below which no accumulation takes place.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
default: 0

8
Documentation/devicetree/bindings/hwmon/baikal,bt1-pvt.yaml
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@ -73,11 +73,9 @@ properties:
description: |
Temperature sensor trimming factor. It can be used to manually adjust the
temperature measurements within 7.130 degrees Celsius.
maxItems: 1
items:
default: 0
minimum: 0
maximum: 7130
default: 0
minimum: 0
maximum: 7130
additionalProperties: false

1
Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml
View File

@ -52,7 +52,6 @@ properties:
ti,bus-range-microvolt:
description: |
This is the operating range of the bus voltage in microvolt
$ref: /schemas/types.yaml#/definitions/uint32
enum: [16000000, 32000000]
default: 32000000

2
Documentation/devicetree/bindings/i2c/i2c-gpio.yaml
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@ -39,11 +39,9 @@ properties:
i2c-gpio,delay-us:
description: delay between GPIO operations (may depend on each platform)
$ref: /schemas/types.yaml#/definitions/uint32
i2c-gpio,timeout-ms:
description: timeout to get data
$ref: /schemas/types.yaml#/definitions/uint32
# Deprecated properties, do not use in new device tree sources:
gpios:

3
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
View File

@ -66,21 +66,18 @@ properties:
default: 400000
i2c-sda-hold-time-ns:
maxItems: 1
description: |
The property should contain the SDA hold time in nanoseconds. This option
is only supported in hardware blocks version 1.11a or newer or on
Microsemi SoCs.
i2c-scl-falling-time-ns:
maxItems: 1
description: |
The property should contain the SCL falling time in nanoseconds.
This value is used to compute the tLOW period.
default: 300
i2c-sda-falling-time-ns:
maxItems: 1
description: |
The property should contain the SDA falling time in nanoseconds.
This value is used to compute the tHIGH period.

2
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
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@ -80,7 +80,7 @@ properties:
type: boolean
bipolar:
description: see Documentation/devicetree/bindings/iio/adc/adc.txt
description: see Documentation/devicetree/bindings/iio/adc/adc.yaml
type: boolean
required:

1
Documentation/devicetree/bindings/iio/adc/maxim,max9611.yaml
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@ -23,7 +23,6 @@ properties:
maxItems: 1
shunt-resistor-micro-ohms:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Value in micro Ohms of the shunt resistor connected between the RS+ and
RS- inputs, across which the current is measured. Value needed to compute

1
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
View File

@ -246,7 +246,6 @@ patternProperties:
Resolution (bits) to use for conversions:
- can be 6, 8, 10 or 12 on stm32f4
- can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
$ref: /schemas/types.yaml#/definitions/uint32
st,adc-channels:
description: |

2
Documentation/devicetree/bindings/iio/adc/ti,palmas-gpadc.yaml
View File

@ -42,7 +42,6 @@ properties:
const: 1
ti,channel0-current-microamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: Channel 0 current in uA.
enum:
- 0
@ -51,7 +50,6 @@ properties:
- 20
ti,channel3-current-microamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: Channel 3 current in uA.
enum:
- 0

41
Documentation/devicetree/bindings/iio/dac/adi,ad5758.yaml
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@ -46,31 +46,42 @@ properties:
two properties must be present:
adi,range-microvolt:
$ref: /schemas/types.yaml#/definitions/int32-array
description: |
Voltage output range specified as <minimum, maximum>
enum:
- [[0, 5000000]]
- [[0, 10000000]]
- [[-5000000, 5000000]]
- [[-10000000, 10000000]]
oneOf:
- items:
- const: 0
- enum: [5000000, 10000000]
- items:
- const: -5000000
- const: 5000000
- items:
- const: -10000000
- const: 10000000
adi,range-microamp:
$ref: /schemas/types.yaml#/definitions/int32-array
description: |
Current output range specified as <minimum, maximum>
enum:
- [[0, 20000]]
- [[0, 24000]]
- [[4, 24000]]
- [[-20000, 20000]]
- [[-24000, 24000]]
- [[-1000, 22000]]
oneOf:
- items:
- const: 0
- enum: [20000, 24000]
- items:
- const: 4
- const: 24000
- items:
- const: -20000
- const: 20000
- items:
- const: -24000
- const: 24000
- items:
- const: -1000
- const: 22000
reset-gpios: true
adi,dc-dc-ilim-microamp:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [150000, 200000, 250000, 300000, 350000, 400000]
description: |
The dc-to-dc converter current limit.

1
Documentation/devicetree/bindings/iio/health/maxim,max30100.yaml
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@ -21,7 +21,6 @@ properties:
description: Connected to ADC_RDY pin.
maxim,led-current-microamp:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
description: |

2
Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml
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@ -70,11 +70,9 @@ properties:
touchscreen-x-mm:
description: horizontal length in mm of the touchscreen
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-y-mm:
description: vertical length in mm of the touchscreen
$ref: /schemas/types.yaml#/definitions/uint32
dependencies:
touchscreen-size-x: [ touchscreen-size-y ]

111
Documentation/devicetree/bindings/leds/richtek,rt8515.yaml Normal file
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@ -0,0 +1,111 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/richtek,rt8515.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Richtek RT8515 1.5A dual channel LED driver
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The Richtek RT8515 is a dual channel (two mode) LED driver that
supports driving a white LED in flash or torch mode. The maximum
current for each mode is defined in hardware using two resistors
RFS and RTS.
properties:
compatible:
const: richtek,rt8515
enf-gpios:
maxItems: 1
description: A connection to the 'ENF' (enable flash) pin.
ent-gpios:
maxItems: 1
description: A connection to the 'ENT' (enable torch) pin.
richtek,rfs-ohms:
minimum: 7680
maximum: 367000
description: The resistance value of the RFS resistor. This
resistors limits the maximum flash current. This must be set
for the property flash-max-microamp to work, the RFS resistor
defines the range of the dimmer setting (brightness) of the
flash LED.
richtek,rts-ohms:
minimum: 7680
maximum: 367000
description: The resistance value of the RTS resistor. This
resistors limits the maximum torch current. This must be set
for the property torch-max-microamp to work, the RTS resistor
defines the range of the dimmer setting (brightness) of the
torch LED.
led:
type: object
$ref: common.yaml#
properties:
function: true
color: true
flash-max-timeout-us: true
flash-max-microamp:
maximum: 700000
description: The maximum current for flash mode
is hardwired to the component using the RFS resistor to
ground. The maximum hardware current setting is calculated
according to the formula Imax = 5500 / RFS. The lowest
allowed resistance value is 7.86 kOhm giving an absolute
maximum current of 700mA. By setting this attribute in
the device tree, you can further restrict the maximum
current below the hardware limit. This requires the RFS
to be defined as it defines the maximum range.
led-max-microamp:
maximum: 700000
description: The maximum current for torch mode
is hardwired to the component using the RTS resistor to
ground. The maximum hardware current setting is calculated
according to the formula Imax = 5500 / RTS. The lowest
allowed resistance value is 7.86 kOhm giving an absolute
maximum current of 700mA. By setting this attribute in
the device tree, you can further restrict the maximum
current below the hardware limit. This requires the RTS
to be defined as it defines the maximum range.
additionalProperties: false
required:
- compatible
- ent-gpios
- enf-gpios
- led
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
led-controller {
compatible = "richtek,rt8515";
enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
richtek,rfs-ohms = <16000>;
richtek,rts-ohms = <100000>;
led {
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
flash-max-timeout-us = <250000>;
flash-max-microamp = <150000>;
led-max-microamp = <25000>;
};
};
...

2
Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
View File

@ -16,7 +16,7 @@ Required properties:
- power-domains: a phandle to the power domain, see
Documentation/devicetree/bindings/power/power_domain.txt for details.
- mediatek,larb: must contain the local arbiters in the current Socs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

2
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
View File

@ -14,7 +14,7 @@ Required properties:
- power-domains: a phandle to the power domain, see
Documentation/devicetree/bindings/power/power_domain.txt for details.
- mediatek,larb: must contain the local arbiters in the current SoCs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

2
Documentation/devicetree/bindings/media/mediatek-mdp.txt
View File

@ -28,7 +28,7 @@ Required properties (DMA function blocks, child node):
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
- mediatek,larb: must contain the local arbiters in the current Socs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
Example:

1
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
View File

@ -259,7 +259,6 @@ properties:
waiting for I/O signalling and card power supply to be stable,
regardless of whether pwrseq-simple is used. Default to 10ms if
no available.
$ref: /schemas/types.yaml#/definitions/uint32
default: 10
supports-cqe:

2
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml
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@ -41,13 +41,11 @@ properties:
description:
Delay in ms after powering the card and de-asserting the
reset-gpios (if any).
$ref: /schemas/types.yaml#/definitions/uint32
power-off-delay-us:
description:
Delay in us after asserting the reset-gpios (if any)
during power off of the card.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible

2
Documentation/devicetree/bindings/net/ethernet-controller.yaml
View File

@ -122,7 +122,6 @@ properties:
such as flow control thresholds.
rx-internal-delay-ps:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Receive Clock Delay defined in pico seconds.
This is used for controllers that have configurable RX internal delays.
@ -140,7 +139,6 @@ properties:
is used for components that can have configurable fifo sizes.
tx-internal-delay-ps:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Transmit Clock Delay defined in pico seconds.
This is used for controllers that have configurable TX internal delays.

1
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@ -212,7 +212,6 @@ properties:
Triplet of delays. The 1st cell is reset pre-delay in micro
seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
cell is reset post-delay in micro seconds.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3

3
Documentation/devicetree/bindings/power/supply/battery.yaml
View File

@ -83,21 +83,18 @@ properties:
for each of the battery capacity lookup table.
operating-range-celsius:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: operating temperature range of a battery
items:
- description: minimum temperature at which battery can operate
- description: maximum temperature at which battery can operate
ambient-celsius:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: safe range of ambient temperature
items:
- description: alert when ambient temperature is lower than this value
- description: alert when ambient temperature is higher than this value
alert-celsius:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: safe range of battery temperature
items:
- description: alert when battery temperature is lower than this value

1
Documentation/devicetree/bindings/power/supply/bq2515x.yaml
View File

@ -50,7 +50,6 @@ properties:
maxItems: 1
input-current-limit-microamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: Maximum input current in micro Amps.
minimum: 50000
maximum: 500000

1
Documentation/devicetree/bindings/regulator/dlg,da9121.yaml
View File

@ -62,7 +62,6 @@ properties:
description: IRQ line information.
dlg,irq-polling-delay-passive-ms:
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 1000
maximum: 10000
description: |

2
Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
View File

@ -72,11 +72,9 @@ properties:
startup-delay-us:
description: startup time in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
off-on-delay-us:
description: off delay time in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
enable-active-high:
description:

2
Documentation/devicetree/bindings/rtc/rtc.yaml
View File

@ -27,7 +27,6 @@ properties:
1: chargeable
quartz-load-femtofarads:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The capacitive load of the quartz(x-tal), expressed in femto
Farad (fF). The default value shall be listed (if optional),
@ -47,7 +46,6 @@ properties:
deprecated: true
trickle-resistor-ohms:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selected resistor for trickle charger. Should be given
if trickle charger should be enabled.

2
Documentation/devicetree/bindings/serial/pl011.yaml
View File

@ -88,14 +88,12 @@ properties:
description:
Rate at which poll occurs when auto-poll is set.
default 100ms.
$ref: /schemas/types.yaml#/definitions/uint32
default: 100
poll-timeout-ms:
description:
Poll timeout when auto-poll is set, default
3000ms.
$ref: /schemas/types.yaml#/definitions/uint32
default: 3000
required:

2
Documentation/devicetree/bindings/sound/sgtl5000.yaml
View File

@ -41,14 +41,12 @@ properties:
values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
mentioned or if the value is unknown, then micbias resistor is set to
4k.
$ref: "/schemas/types.yaml#/definitions/uint32"
enum: [ 0, 2, 4, 8 ]
micbias-voltage-m-volts:
description: The bias voltage to be used in mVolts. The voltage can take
values from 1.25V to 3V by 250mV steps. If this node is not mentioned
or the value is unknown, then the value is set to 1.25V.
$ref: "/schemas/types.yaml#/definitions/uint32"
enum: [ 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 ]
lrclk-strength:

4
Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml
View File

@ -21,6 +21,8 @@ properties:
reg:
description: module registers
ranges: true
power-domains:
description:
PM domain provider node and an args specifier containing
@ -62,6 +64,8 @@ properties:
'#size-cells':
const: 2
dma-coherent: true
patternProperties:
"^usb@":
type: object

1
Documentation/devicetree/bindings/watchdog/watchdog.yaml
View File

@ -19,7 +19,6 @@ properties:
pattern: "^watchdog(@.*|-[0-9a-f])?$"
timeout-sec:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Contains the watchdog timeout in seconds.

2
Documentation/networking/ip-sysctl.rst
View File

@ -1196,7 +1196,7 @@ icmp_errors_use_inbound_ifaddr - BOOLEAN
If non-zero, the message will be sent with the primary address of
the interface that received the packet that caused the icmp error.
This is the behaviour network many administrators will expect from
This is the behaviour many network administrators will expect from
a router. And it can make debugging complicated network layouts
much easier.

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 5
PATCHLEVEL = 11
SUBLEVEL = 0
EXTRAVERSION = -rc5
EXTRAVERSION = -rc6
NAME = Kleptomaniac Octopus
# *DOCUMENTATION*

3
arch/arm/boot/compressed/atags_to_fdt.c
View File

@ -15,7 +15,8 @@ static int node_offset(void *fdt, const char *node_path)
{
int offset = fdt_path_offset(fdt, node_path);
if (offset == -FDT_ERR_NOTFOUND)
offset = fdt_add_subnode(fdt, 0, node_path);
/* Add the node to root if not found, dropping the leading '/' */
offset = fdt_add_subnode(fdt, 0, node_path + 1);
return offset;
}

6
arch/arm64/include/asm/memory.h
View File

@ -247,9 +247,11 @@ static inline const void *__tag_set(const void *addr, u8 tag)
/*
* The linear kernel range starts at the bottom of the virtual address space.
* Check whether an arbitrary address is within the linear map, which
* lives in the [PAGE_OFFSET, PAGE_END) interval at the bottom of the
* kernel's TTBR1 address range.
*/
#define __is_lm_address(addr) (((u64)(addr) & ~PAGE_OFFSET) < (PAGE_END - PAGE_OFFSET))
#define __is_lm_address(addr) (((u64)(addr) ^ PAGE_OFFSET) < (PAGE_END - PAGE_OFFSET))
#define __lm_to_phys(addr) (((addr) & ~PAGE_OFFSET) + PHYS_OFFSET)
#define __kimg_to_phys(addr) ((addr) - kimage_voffset)

30
arch/powerpc/kernel/irq.c
View File

@ -180,14 +180,19 @@ void notrace restore_interrupts(void)
void replay_soft_interrupts(void)
{
/*
* We use local_paca rather than get_paca() to avoid all
* the debug_smp_processor_id() business in this low level
* function
*/
unsigned char happened = local_paca->irq_happened;
struct pt_regs regs;
/*
* Be careful here, calling these interrupt handlers can cause
* softirqs to be raised, which they may run when calling irq_exit,
* which will cause local_irq_enable() to be run, which can then
* recurse into this function. Don't keep any state across
* interrupt handler calls which may change underneath us.
*
* We use local_paca rather than get_paca() to avoid all the
* debug_smp_processor_id() business in this low level function.
*/
ppc_save_regs(&regs);
regs.softe = IRQS_ENABLED;
@ -209,7 +214,7 @@ again:
* This is a higher priority interrupt than the others, so
* replay it first.
*/
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_HMI)) {
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_HMI)) {
local_paca->irq_happened &= ~PACA_IRQ_HMI;
regs.trap = 0xe60;
handle_hmi_exception(&regs);
@ -217,7 +222,7 @@ again:
hard_irq_disable();
}
if (happened & PACA_IRQ_DEC) {
if (local_paca->irq_happened & PACA_IRQ_DEC) {
local_paca->irq_happened &= ~PACA_IRQ_DEC;
regs.trap = 0x900;
timer_interrupt(&regs);
@ -225,7 +230,7 @@ again:
hard_irq_disable();
}
if (happened & PACA_IRQ_EE) {
if (local_paca->irq_happened & PACA_IRQ_EE) {
local_paca->irq_happened &= ~PACA_IRQ_EE;
regs.trap = 0x500;
do_IRQ(&regs);
@ -233,7 +238,7 @@ again:
hard_irq_disable();
}
if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (happened & PACA_IRQ_DBELL)) {
if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (local_paca->irq_happened & PACA_IRQ_DBELL)) {
local_paca->irq_happened &= ~PACA_IRQ_DBELL;
if (IS_ENABLED(CONFIG_PPC_BOOK3E))
regs.trap = 0x280;
@ -245,7 +250,7 @@ again:
}
/* Book3E does not support soft-masking PMI interrupts */
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_PMI)) {
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_PMI)) {
local_paca->irq_happened &= ~PACA_IRQ_PMI;
regs.trap = 0xf00;
performance_monitor_exception(&regs);
@ -253,8 +258,7 @@ again:
hard_irq_disable();
}
happened = local_paca->irq_happened;
if (happened & ~PACA_IRQ_HARD_DIS) {
if (local_paca->irq_happened & ~PACA_IRQ_HARD_DIS) {
/*
* We are responding to the next interrupt, so interrupt-off
* latencies should be reset here.

2
arch/riscv/mm/init.c
View File

@ -196,7 +196,7 @@ void __init setup_bootmem(void)
max_pfn = PFN_DOWN(dram_end);
max_low_pfn = max_pfn;
dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn));
set_max_mapnr(max_low_pfn);
set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET);
#ifdef CONFIG_BLK_DEV_INITRD
setup_initrd();

2
arch/s390/boot/uv.c
View File

@ -35,7 +35,7 @@ void uv_query_info(void)
uv_info.guest_cpu_stor_len = uvcb.cpu_stor_len;
uv_info.max_sec_stor_addr = ALIGN(uvcb.max_guest_stor_addr, PAGE_SIZE);
uv_info.max_num_sec_conf = uvcb.max_num_sec_conf;
uv_info.max_guest_cpus = uvcb.max_guest_cpus;
uv_info.max_guest_cpu_id = uvcb.max_guest_cpu_id;
}
#ifdef CONFIG_PROTECTED_VIRTUALIZATION_GUEST

4
arch/s390/include/asm/uv.h
View File

@ -96,7 +96,7 @@ struct uv_cb_qui {
u32 max_num_sec_conf;
u64 max_guest_stor_addr;
u8 reserved88[158 - 136];
u16 max_guest_cpus;
u16 max_guest_cpu_id;
u8 reserveda0[200 - 160];
} __packed __aligned(8);
@ -273,7 +273,7 @@ struct uv_info {
unsigned long guest_cpu_stor_len;
unsigned long max_sec_stor_addr;
unsigned int max_num_sec_conf;
unsigned short max_guest_cpus;
unsigned short max_guest_cpu_id;
};
extern struct uv_info uv_info;

2
arch/s390/kernel/uv.c
View File

@ -368,7 +368,7 @@ static ssize_t uv_query_max_guest_cpus(struct kobject *kobj,
struct kobj_attribute *attr, char *page)
{
return scnprintf(page, PAGE_SIZE, "%d\n",
uv_info.max_guest_cpus);
uv_info.max_guest_cpu_id + 1);
}
static struct kobj_attribute uv_query_max_guest_cpus_attr =

15
arch/x86/entry/thunk_64.S
View File

@ -10,7 +10,7 @@
#include <asm/export.h>
/* rdi: arg1 ... normal C conventions. rax is saved/restored. */
.macro THUNK name, func, put_ret_addr_in_rdi=0
.macro THUNK name, func
SYM_FUNC_START_NOALIGN(\name)
pushq %rbp
movq %rsp, %rbp
@ -25,13 +25,8 @@ SYM_FUNC_START_NOALIGN(\name)
pushq %r10
pushq %r11
.if \put_ret_addr_in_rdi
/* 8(%rbp) is return addr on stack */
movq 8(%rbp), %rdi
.endif
call \func
jmp .L_restore
jmp __thunk_restore
SYM_FUNC_END(\name)
_ASM_NOKPROBE(\name)
.endm
@ -44,7 +39,7 @@ SYM_FUNC_END(\name)
#endif
#ifdef CONFIG_PREEMPTION
SYM_CODE_START_LOCAL_NOALIGN(.L_restore)
SYM_CODE_START_LOCAL_NOALIGN(__thunk_restore)
popq %r11
popq %r10
popq %r9
@ -56,6 +51,6 @@ SYM_CODE_START_LOCAL_NOALIGN(.L_restore)
popq %rdi
popq %rbp
ret
_ASM_NOKPROBE(.L_restore)
SYM_CODE_END(.L_restore)
_ASM_NOKPROBE(__thunk_restore)
SYM_CODE_END(__thunk_restore)
#endif

18
block/blk-cgroup.c
View File

@ -1016,6 +1016,8 @@ static void blkcg_css_offline(struct cgroup_subsys_state *css)
*/
void blkcg_destroy_blkgs(struct blkcg *blkcg)
{
might_sleep();
spin_lock_irq(&blkcg->lock);
while (!hlist_empty(&blkcg->blkg_list)) {
@ -1023,14 +1025,20 @@ void blkcg_destroy_blkgs(struct blkcg *blkcg)
struct blkcg_gq, blkcg_node);
struct request_queue *q = blkg->q;
if (spin_trylock(&q->queue_lock)) {
blkg_destroy(blkg);
spin_unlock(&q->queue_lock);
} else {
if (need_resched() || !spin_trylock(&q->queue_lock)) {
/*
* Given that the system can accumulate a huge number
* of blkgs in pathological cases, check to see if we
* need to rescheduling to avoid softlockup.
*/
spin_unlock_irq(&blkcg->lock);
cpu_relax();
cond_resched();
spin_lock_irq(&blkcg->lock);
continue;
}
blkg_destroy(blkg);
spin_unlock(&q->queue_lock);
}
spin_unlock_irq(&blkcg->lock);

2
block/blk-mq.h
View File

@ -304,7 +304,7 @@ static inline bool hctx_may_queue(struct blk_mq_hw_ctx *hctx,
struct request_queue *q = hctx->queue;
struct blk_mq_tag_set *set = q->tag_set;
if (!test_bit(BLK_MQ_S_TAG_ACTIVE, &q->queue_flags))
if (!test_bit(QUEUE_FLAG_HCTX_ACTIVE, &q->queue_flags))
return true;
users = atomic_read(&set->active_queues_shared_sbitmap);
} else {

5
block/genhd.c
View File

@ -45,10 +45,11 @@ static void disk_release_events(struct gendisk *disk);
void set_capacity(struct gendisk *disk, sector_t sectors)
{
struct block_device *bdev = disk->part0;
unsigned long flags;
spin_lock(&bdev->bd_size_lock);
spin_lock_irqsave(&bdev->bd_size_lock, flags);
i_size_write(bdev->bd_inode, (loff_t)sectors << SECTOR_SHIFT);
spin_unlock(&bdev->bd_size_lock);
spin_unlock_irqrestore(&bdev->bd_size_lock, flags);
}
EXPORT_SYMBOL(set_capacity);

8
block/partitions/core.c
View File

@ -88,9 +88,11 @@ static int (*check_part[])(struct parsed_partitions *) = {
static void bdev_set_nr_sectors(struct block_device *bdev, sector_t sectors)
{
spin_lock(&bdev->bd_size_lock);
unsigned long flags;
spin_lock_irqsave(&bdev->bd_size_lock, flags);
i_size_write(bdev->bd_inode, (loff_t)sectors << SECTOR_SHIFT);
spin_unlock(&bdev->bd_size_lock);
spin_unlock_irqrestore(&bdev->bd_size_lock, flags);
}
static struct parsed_partitions *allocate_partitions(struct gendisk *hd)
@ -384,7 +386,7 @@ static struct block_device *add_partition(struct gendisk *disk, int partno,
err = blk_alloc_devt(bdev, &devt);
if (err)
goto out_bdput;
goto out_put;
pdev->devt = devt;
/* delay uevent until 'holders' subdir is created */

14
drivers/acpi/arm64/iort.c
View File

@ -1107,6 +1107,11 @@ static int nc_dma_get_range(struct device *dev, u64 *size)
ncomp = (struct acpi_iort_named_component *)node->node_data;
if (!ncomp->memory_address_limit) {
pr_warn(FW_BUG "Named component missing memory address limit\n");
return -EINVAL;
}
*size = ncomp->memory_address_limit >= 64 ? U64_MAX :
1ULL<<ncomp->memory_address_limit;
@ -1126,6 +1131,11 @@ static int rc_dma_get_range(struct device *dev, u64 *size)
rc = (struct acpi_iort_root_complex *)node->node_data;
if (!rc->memory_address_limit) {
pr_warn(FW_BUG "Root complex missing memory address limit\n");
return -EINVAL;
}
*size = rc->memory_address_limit >= 64 ? U64_MAX :
1ULL<<rc->memory_address_limit;
@ -1173,8 +1183,8 @@ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size)
end = dmaaddr + size - 1;
mask = DMA_BIT_MASK(ilog2(end) + 1);
dev->bus_dma_limit = end;
dev->coherent_dma_mask = mask;
*dev->dma_mask = mask;
dev->coherent_dma_mask = min(dev->coherent_dma_mask, mask);
*dev->dma_mask = min(*dev->dma_mask, mask);
}
*dma_addr = dmaaddr;

20
drivers/acpi/device_sysfs.c
View File

@ -251,20 +251,12 @@ int __acpi_device_uevent_modalias(struct acpi_device *adev,
if (add_uevent_var(env, "MODALIAS="))
return -ENOMEM;
len = create_pnp_modalias(adev, &env->buf[env->buflen - 1],
sizeof(env->buf) - env->buflen);
if (len < 0)
return len;
env->buflen += len;
if (!adev->data.of_compatible)
return 0;
if (len > 0 && add_uevent_var(env, "MODALIAS="))
return -ENOMEM;
len = create_of_modalias(adev, &env->buf[env->buflen - 1],
sizeof(env->buf) - env->buflen);
if (adev->data.of_compatible)
len = create_of_modalias(adev, &env->buf[env->buflen - 1],
sizeof(env->buf) - env->buflen);
else
len = create_pnp_modalias(adev, &env->buf[env->buflen - 1],
sizeof(env->buf) - env->buflen);
if (len < 0)
return len;

46
drivers/acpi/thermal.c
View File

@ -174,6 +174,8 @@ struct acpi_thermal {
struct thermal_zone_device *thermal_zone;
int kelvin_offset; /* in millidegrees */
struct work_struct thermal_check_work;
struct mutex thermal_check_lock;
refcount_t thermal_check_count;
};
/* --------------------------------------------------------------------------
@ -495,14 +497,6 @@ static int acpi_thermal_get_trip_points(struct acpi_thermal *tz)
return 0;
}
static void acpi_thermal_check(void *data)
{
struct acpi_thermal *tz = data;
thermal_zone_device_update(tz->thermal_zone,
THERMAL_EVENT_UNSPECIFIED);
}
/* sys I/F for generic thermal sysfs support */
static int thermal_get_temp(struct thermal_zone_device *thermal, int *temp)
@ -900,6 +894,12 @@ static void acpi_thermal_unregister_thermal_zone(struct acpi_thermal *tz)
Driver Interface
-------------------------------------------------------------------------- */
static void acpi_queue_thermal_check(struct acpi_thermal *tz)
{
if (!work_pending(&tz->thermal_check_work))
queue_work(acpi_thermal_pm_queue, &tz->thermal_check_work);
}
static void acpi_thermal_notify(struct acpi_device *device, u32 event)
{
struct acpi_thermal *tz = acpi_driver_data(device);
@ -910,17 +910,17 @@ static void acpi_thermal_notify(struct acpi_device *device, u32 event)
switch (event) {
case ACPI_THERMAL_NOTIFY_TEMPERATURE:
acpi_thermal_check(tz);
acpi_queue_thermal_check(tz);
break;
case ACPI_THERMAL_NOTIFY_THRESHOLDS:
acpi_thermal_trips_update(tz, ACPI_TRIPS_REFRESH_THRESHOLDS);
acpi_thermal_check(tz);
acpi_queue_thermal_check(tz);
acpi_bus_generate_netlink_event(device->pnp.device_class,
dev_name(&device->dev), event, 0);
break;
case ACPI_THERMAL_NOTIFY_DEVICES:
acpi_thermal_trips_update(tz, ACPI_TRIPS_REFRESH_DEVICES);
acpi_thermal_check(tz);
acpi_queue_thermal_check(tz);
acpi_bus_generate_netlink_event(device->pnp.device_class,
dev_name(&device->dev), event, 0);
break;
@ -1020,7 +1020,25 @@ static void acpi_thermal_check_fn(struct work_struct *work)
{
struct acpi_thermal *tz = container_of(work, struct acpi_thermal,
thermal_check_work);
acpi_thermal_check(tz);
/*
* In general, it is not sufficient to check the pending bit, because
* subsequent instances of this function may be queued after one of them
* has started running (e.g. if _TMP sleeps). Avoid bailing out if just
* one of them is running, though, because it may have done the actual
* check some time ago, so allow at least one of them to block on the
* mutex while another one is running the update.
*/
if (!refcount_dec_not_one(&tz->thermal_check_count))
return;
mutex_lock(&tz->thermal_check_lock);
thermal_zone_device_update(tz->thermal_zone, THERMAL_EVENT_UNSPECIFIED);
refcount_inc(&tz->thermal_check_count);
mutex_unlock(&tz->thermal_check_lock);
}
static int acpi_thermal_add(struct acpi_device *device)
@ -1052,6 +1070,8 @@ static int acpi_thermal_add(struct acpi_device *device)
if (result)
goto free_memory;
refcount_set(&tz->thermal_check_count, 3);
mutex_init(&tz->thermal_check_lock);
INIT_WORK(&tz->thermal_check_work, acpi_thermal_check_fn);
pr_info(PREFIX "%s [%s] (%ld C)\n", acpi_device_name(device),
@ -1117,7 +1137,7 @@ static int acpi_thermal_resume(struct device *dev)
tz->state.active |= tz->trips.active[i].flags.enabled;
}
queue_work(acpi_thermal_pm_queue, &tz->thermal_check_work);
acpi_queue_thermal_check(tz);
return AE_OK;
}

8
drivers/block/nbd.c
View File

@ -1022,6 +1022,12 @@ static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg,
if (!sock)
return err;
/*
* We need to make sure we don't get any errant requests while we're
* reallocating the ->socks array.
*/
blk_mq_freeze_queue(nbd->disk->queue);
if (!netlink && !nbd->task_setup &&
!test_bit(NBD_RT_BOUND, &config->runtime_flags))
nbd->task_setup = current;
@ -1060,10 +1066,12 @@ static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg,
nsock->cookie = 0;
socks[config->num_connections++] = nsock;
atomic_inc(&config->live_connections);
blk_mq_unfreeze_queue(nbd->disk->queue);
return 0;
put_socket:
blk_mq_unfreeze_queue(nbd->disk->queue);
sockfd_put(sock);
return err;
}

16
drivers/block/null_blk/zoned.c
View File

@ -6,7 +6,10 @@
#define CREATE_TRACE_POINTS
#include "trace.h"
#define MB_TO_SECTS(mb) (((sector_t)mb * SZ_1M) >> SECTOR_SHIFT)
static inline sector_t mb_to_sects(unsigned long mb)
{
return ((sector_t)mb * SZ_1M) >> SECTOR_SHIFT;
}
static inline unsigned int null_zone_no(struct nullb_device *dev, sector_t sect)
{
@ -77,12 +80,11 @@ int null_init_zoned_dev(struct nullb_device *dev, struct request_queue *q)
return -EINVAL;
}
zone_capacity_sects = MB_TO_SECTS(dev->zone_capacity);
dev_capacity_sects = MB_TO_SECTS(dev->size);
dev->zone_size_sects = MB_TO_SECTS(dev->zone_size);
dev->nr_zones = dev_capacity_sects >> ilog2(dev->zone_size_sects);
if (dev_capacity_sects & (dev->zone_size_sects - 1))
dev->nr_zones++;
zone_capacity_sects = mb_to_sects(dev->zone_capacity);
dev_capacity_sects = mb_to_sects(dev->size);
dev->zone_size_sects = mb_to_sects(dev->zone_size);
dev->nr_zones = round_up(dev_capacity_sects, dev->zone_size_sects)
>> ilog2(dev->zone_size_sects);
dev->zones = kvmalloc_array(dev->nr_zones, sizeof(struct nullb_zone),
GFP_KERNEL | __GFP_ZERO);

13
drivers/firmware/efi/apple-properties.c
View File

@ -3,8 +3,9 @@
* apple-properties.c - EFI device properties on Macs
* Copyright (C) 2016 Lukas Wunner <lukas@wunner.de>
*
* Note, all properties are considered as u8 arrays.
* To get a value of any of them the caller must use device_property_read_u8_array().
* Properties are stored either as:
* u8 arrays which can be retrieved with device_property_read_u8_array() or
* booleans which can be queried with device_property_present().
*/
#define pr_fmt(fmt) "apple-properties: " fmt
@ -88,8 +89,12 @@ static void __init unmarshal_key_value_pairs(struct dev_header *dev_header,
entry_data = ptr + key_len + sizeof(val_len);
entry_len = val_len - sizeof(val_len);
entry[i] = PROPERTY_ENTRY_U8_ARRAY_LEN(key, entry_data,
entry_len);
if (entry_len)
entry[i] = PROPERTY_ENTRY_U8_ARRAY_LEN(key, entry_data,
entry_len);
else
entry[i] = PROPERTY_ENTRY_BOOL(key);
if (dump_properties) {
dev_info(dev, "property: %s\n", key);
print_hex_dump(KERN_INFO, pr_fmt(), DUMP_PREFIX_OFFSET,

6
drivers/gpu/drm/amd/display/dc/dcn30/Makefile
View File

@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \
ifdef CONFIG_X86
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse
endif
ifdef CONFIG_PPC64
@ -45,6 +45,8 @@ ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
IS_OLD_GCC = 1
endif
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float
endif
ifdef CONFIG_X86

3
drivers/gpu/drm/amd/display/dc/dcn301/Makefile
View File

@ -14,7 +14,7 @@ DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o
ifdef CONFIG_X86
CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -msse
CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -msse
endif
ifdef CONFIG_PPC64
@ -25,6 +25,7 @@ ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
IS_OLD_GCC = 1
endif
CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -mhard-float
endif
ifdef CONFIG_X86

3
drivers/gpu/drm/amd/display/dc/dcn302/Makefile
View File

@ -13,7 +13,7 @@
DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
ifdef CONFIG_X86
CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse
endif
ifdef CONFIG_PPC64
@ -24,6 +24,7 @@ ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
IS_OLD_GCC = 1
endif
CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -mhard-float
endif
ifdef CONFIG_X86

1
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
View File

@ -553,6 +553,7 @@ struct pptable_funcs {
*clock_req);
uint32_t (*get_fan_control_mode)(struct smu_context *smu);
int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
int (*gfx_off_control)(struct smu_context *smu, bool enable);

3
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
View File

@ -203,6 +203,9 @@ int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode);
int
smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
uint32_t speed);

9
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -2151,19 +2151,14 @@ int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
{
int ret = 0;
uint32_t rpm;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->set_fan_speed_rpm) {
if (speed > 100)
speed = 100;
rpm = speed * smu->fan_max_rpm / 100;
ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
}
if (smu->ppt_funcs->set_fan_speed_percent)
ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
mutex_unlock(&smu->mutex);

1
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
View File

@ -2326,6 +2326,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,

1
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -2456,6 +2456,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,

1
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -2802,6 +2802,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,

31
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
View File

@ -1173,6 +1173,35 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
return 0;
}
int
smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
{
struct amdgpu_device *adev = smu->adev;
uint32_t duty100, duty;
uint64_t tmp64;
if (speed > 100)
speed = 100;
if (smu_v11_0_auto_fan_control(smu, 0))
return -EINVAL;
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
CG_FDO_CTRL1, FMAX_DUTY100);
if (!duty100)
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
do_div(tmp64, 100);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
}
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
@ -1181,7 +1210,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
ret = smu_v11_0_set_fan_speed_percent(smu, 100);
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v11_0_auto_fan_control(smu, 0);

7
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -2755,12 +2755,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
u32 val;
ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
/* The table does not have values for level 3 and level 9. */
if (level >= n_entries || level == 3 || level == 9) {
if (level >= n_entries) {
drm_dbg_kms(&dev_priv->drm,
"DDI translation not found for level %d. Using %d instead.",
level, n_entries - 2);
level = n_entries - 2;
level, n_entries - 1);
level = n_entries - 1;
}
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */

12
drivers/gpu/drm/i915/gt/gen7_renderclear.c
View File

@ -390,6 +390,16 @@ static void emit_batch(struct i915_vma * const vma,
&cb_kernel_ivb,
desc_count);
/* Reset inherited context registers */
gen7_emit_pipeline_invalidate(&cmds);
batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
batch_add(&cmds, 0xffff0000);
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
gen7_emit_pipeline_flush(&cmds);
/* Switch to the media pipeline and our base address */
gen7_emit_pipeline_invalidate(&cmds);
batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
batch_add(&cmds, MI_NOOP);
@ -399,9 +409,11 @@ static void emit_batch(struct i915_vma * const vma,
gen7_emit_state_base_address(&cmds, descriptors);
gen7_emit_pipeline_invalidate(&cmds);
/* Set the clear-residual kernel state */
gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
/* Execute the kernel on all HW threads */
for (i = 0; i < num_primitives(bv); i++)
gen7_emit_media_object(&cmds, i);

47
drivers/gpu/drm/i915/gt/intel_ggtt.c
View File

@ -526,16 +526,39 @@ static int init_ggtt(struct i915_ggtt *ggtt)
mutex_init(&ggtt->error_mutex);
if (ggtt->mappable_end) {
/* Reserve a mappable slot for our lockless error capture */
ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
0, ggtt->mappable_end,
DRM_MM_INSERT_LOW);
if (ret)
return ret;
/*
* Reserve a mappable slot for our lockless error capture.
*
* We strongly prefer taking address 0x0 in order to protect
* other critical buffers against accidental overwrites,
* as writing to address 0 is a very common mistake.
*
* Since 0 may already be in use by the system (e.g. the BIOS
* framebuffer), we let the reservation fail quietly and hope
* 0 remains reserved always.
*
* If we fail to reserve 0, and then fail to find any space
* for an error-capture, remain silent. We can afford not
* to reserve an error_capture node as we have fallback
* paths, and we trust that 0 will remain reserved. However,
* the only likely reason for failure to insert is a driver
* bug, which we expect to cause other failures...
*/
ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
ggtt->error_capture.size, 0,
ggtt->error_capture.color,
0, ggtt->mappable_end,
DRM_MM_INSERT_LOW);
}
if (drm_mm_node_allocated(&ggtt->error_capture))
drm_dbg(&ggtt->vm.i915->drm,
"Reserved GGTT:[%llx, %llx] for use by error capture\n",
ggtt->error_capture.start,
ggtt->error_capture.start + ggtt->error_capture.size);
/*
* The upper portion of the GuC address space has a sizeable hole
@ -548,9 +571,9 @@ static int init_ggtt(struct i915_ggtt *ggtt)
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
drm_dbg_kms(&ggtt->vm.i915->drm,
"clearing unused GTT space: [%lx, %lx]\n",
hole_start, hole_end);
drm_dbg(&ggtt->vm.i915->drm,
"clearing unused GTT space: [%lx, %lx]\n",
hole_start, hole_end);
ggtt->vm.clear_range(&ggtt->vm, hole_start,
hole_end - hole_start);
}

28
drivers/gpu/drm/i915/i915_active.c
View File

@ -631,24 +631,26 @@ static int flush_lazy_signals(struct i915_active *ref)
int __i915_active_wait(struct i915_active *ref, int state)
{
int err;
might_sleep();
if (!i915_active_acquire_if_busy(ref))
return 0;
/* Any fence added after the wait begins will not be auto-signaled */
err = flush_lazy_signals(ref);
i915_active_release(ref);
if (err)
return err;
if (i915_active_acquire_if_busy(ref)) {
int err;
if (!i915_active_is_idle(ref) &&
___wait_var_event(ref, i915_active_is_idle(ref),
state, 0, 0, schedule()))
return -EINTR;
err = flush_lazy_signals(ref);
i915_active_release(ref);
if (err)
return err;
if (___wait_var_event(ref, i915_active_is_idle(ref),
state, 0, 0, schedule()))
return -EINTR;
}
/*
* After the wait is complete, the caller may free the active.
* We have to flush any concurrent retirement before returning.
*/
flush_work(&ref->work);
return 0;
}

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1346,7 +1346,7 @@ intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
{
const unsigned int pi = __platform_mask_index(info, p);
return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
return info->platform_mask[pi] & ((1 << INTEL_SUBPLATFORM_BITS) - 1);
}
static __always_inline bool

2
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
View File

@ -1880,7 +1880,7 @@ static int igt_cs_tlb(void *arg)
vma = i915_vma_instance(out, vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto out_put_batch;
goto out_put_out;
}
err = i915_vma_pin(vma, 0, 0,

6
drivers/gpu/drm/nouveau/dispnv50/base507c.c
View File

@ -88,7 +88,11 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
NVVAL(NV507C, SET_CONVERSION, OFS, 0x64));
} else {
PUSH_MTHD(push, NV507C, SET_PROCESSING,
NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));
NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE),
SET_CONVERSION,
NVVAL(NV507C, SET_CONVERSION, GAIN, 0) |
NVVAL(NV507C, SET_CONVERSION, OFS, 0));
}
PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);

6
drivers/gpu/drm/nouveau/dispnv50/base827c.c
View File

@ -49,7 +49,11 @@ base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
NVVAL(NV827C, SET_CONVERSION, OFS, 0x64));
} else {
PUSH_MTHD(push, NV827C, SET_PROCESSING,
NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));
NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE),
SET_CONVERSION,
NVVAL(NV827C, SET_CONVERSION, GAIN, 0) |
NVVAL(NV827C, SET_CONVERSION, OFS, 0));
}
PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,

8
drivers/gpu/drm/nouveau/dispnv50/disp.c
View File

@ -2663,6 +2663,14 @@ nv50_display_create(struct drm_device *dev)
else
nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
if (disp->disp->object.oclass >= GK104_DISP) {
dev->mode_config.cursor_width = 256;
dev->mode_config.cursor_height = 256;
} else {
dev->mode_config.cursor_width = 64;
dev->mode_config.cursor_height = 64;
}
/* create crtc objects to represent the hw heads */
if (disp->disp->object.oclass >= GV100_DISP)
crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;

28
drivers/gpu/drm/nouveau/dispnv50/head917d.c
View File

@ -22,6 +22,7 @@
#include "head.h"
#include "core.h"
#include "nvif/push.h"
#include <nvif/push507c.h>
#include <nvhw/class/cl917d.h>
@ -73,6 +74,31 @@ head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
return 0;
}
static int
head917d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
{
struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
const int i = head->base.index;
int ret;
ret = PUSH_WAIT(push, 5);
if (ret)
return ret;
PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),
HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
return 0;
}
int
head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw,
struct nv50_head_atom *asyh)
@ -101,7 +127,7 @@ head917d = {
.core_clr = head907d_core_clr,
.curs_layout = head917d_curs_layout,
.curs_format = head507d_curs_format,
.curs_set = head907d_curs_set,
.curs_set = head917d_curs_set,
.curs_clr = head907d_curs_clr,
.base = head917d_base,
.ovly = head907d_ovly,

17
drivers/gpu/drm/nouveau/dispnv50/wndw.c
View File

@ -702,6 +702,11 @@ nv50_wndw_init(struct nv50_wndw *wndw)
nvif_notify_get(&wndw->notify);
}
static const u64 nv50_cursor_format_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID,
};
int
nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
enum drm_plane_type type, const char *name, int index,
@ -713,6 +718,7 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
struct nvif_mmu *mmu = &drm->client.mmu;
struct nv50_disp *disp = nv50_disp(dev);
struct nv50_wndw *wndw;
const u64 *format_modifiers;
int nformat;
int ret;
@ -728,10 +734,13 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
for (nformat = 0; format[nformat]; nformat++);
ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw,
format, nformat,
nouveau_display(dev)->format_modifiers,
type, "%s-%d", name, index);
if (type == DRM_PLANE_TYPE_CURSOR)
format_modifiers = nv50_cursor_format_modifiers;
else
format_modifiers = nouveau_display(dev)->format_modifiers;
ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, format, nformat,
format_modifiers, type, "%s-%d", name, index);
if (ret) {
kfree(*pwndw);
*pwndw = NULL;

4
drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h
View File

@ -66,6 +66,10 @@
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV917D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300)
#define NV917D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)

216
drivers/gpu/drm/nouveau/include/nvif/push.h
View File

@ -123,131 +123,131 @@ PUSH_KICK(struct nvif_push *push)
} while(0)
#endif
#define PUSH_1(X,f,ds,n,c,o,p,s,mA,dA) do { \
PUSH_##o##_HDR((p), s, mA, (c)+(n)); \
PUSH_##f(X, (p), X##mA, 1, o, (dA), ds, ""); \
#define PUSH_1(X,f,ds,n,o,p,s,mA,dA) do { \
PUSH_##o##_HDR((p), s, mA, (ds)+(n)); \
PUSH_##f(X, (p), X##mA, 1, o, (dA), ds, ""); \
} while(0)
#define PUSH_2(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (1?PUSH_##o##_INC), "mthd1"); \
PUSH_1(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_2(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (1?PUSH_##o##_INC), "mthd1"); \
PUSH_1(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_3(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd2"); \
PUSH_2(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_3(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd2"); \
PUSH_2(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_4(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd3"); \
PUSH_3(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_4(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd3"); \
PUSH_3(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_5(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd4"); \
PUSH_4(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_5(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd4"); \
PUSH_4(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_6(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd5"); \
PUSH_5(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_6(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd5"); \
PUSH_5(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_7(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd6"); \
PUSH_6(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_7(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd6"); \
PUSH_6(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_8(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd7"); \
PUSH_7(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_8(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd7"); \
PUSH_7(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_9(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd8"); \
PUSH_8(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_9(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd8"); \
PUSH_8(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_10(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd9"); \
PUSH_9(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
#define PUSH_10(X,f,ds,n,o,p,s,mB,dB,mA,dA,a...) do { \
PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd9"); \
PUSH_9(X, DATA_, 1, (ds) + (n), o, (p), s, X##mA, (dA), ##a); \
PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \
} while(0)
#define PUSH_1D(X,o,p,s,mA,dA) \
PUSH_1(X, DATA_, 1, 1, 0, o, (p), s, X##mA, (dA))
#define PUSH_2D(X,o,p,s,mA,dA,mB,dB) \
PUSH_2(X, DATA_, 1, 1, 0, o, (p), s, X##mB, (dB), \
X##mA, (dA))
#define PUSH_3D(X,o,p,s,mA,dA,mB,dB,mC,dC) \
PUSH_3(X, DATA_, 1, 1, 0, o, (p), s, X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_4D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD) \
PUSH_4(X, DATA_, 1, 1, 0, o, (p), s, X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_5D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE) \
PUSH_5(X, DATA_, 1, 1, 0, o, (p), s, X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_1D(X,o,p,s,mA,dA) \
PUSH_1(X, DATA_, 1, 0, o, (p), s, X##mA, (dA))
#define PUSH_2D(X,o,p,s,mA,dA,mB,dB) \
PUSH_2(X, DATA_, 1, 0, o, (p), s, X##mB, (dB), \
X##mA, (dA))
#define PUSH_3D(X,o,p,s,mA,dA,mB,dB,mC,dC) \
PUSH_3(X, DATA_, 1, 0, o, (p), s, X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_4D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD) \
PUSH_4(X, DATA_, 1, 0, o, (p), s, X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_5D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE) \
PUSH_5(X, DATA_, 1, 0, o, (p), s, X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_6D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF) \
PUSH_6(X, DATA_, 1, 1, 0, o, (p), s, X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
PUSH_6(X, DATA_, 1, 0, o, (p), s, X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_7D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG) \
PUSH_7(X, DATA_, 1, 1, 0, o, (p), s, X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
PUSH_7(X, DATA_, 1, 0, o, (p), s, X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_8D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH) \
PUSH_8(X, DATA_, 1, 1, 0, o, (p), s, X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
PUSH_8(X, DATA_, 1, 0, o, (p), s, X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_9D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,dI) \
PUSH_9(X, DATA_, 1, 1, 0, o, (p), s, X##mI, (dI), \
X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
PUSH_9(X, DATA_, 1, 0, o, (p), s, X##mI, (dI), \
X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_10D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,dI,mJ,dJ) \
PUSH_10(X, DATA_, 1, 1, 0, o, (p), s, X##mJ, (dJ), \
X##mI, (dI), \
X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
PUSH_10(X, DATA_, 1, 0, o, (p), s, X##mJ, (dJ), \
X##mI, (dI), \
X##mH, (dH), \
X##mG, (dG), \
X##mF, (dF), \
X##mE, (dE), \
X##mD, (dD), \
X##mC, (dC), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_1P(X,o,p,s,mA,dp,ds) \
PUSH_1(X, DATAp, ds, ds, 0, o, (p), s, X##mA, (dp))
#define PUSH_2P(X,o,p,s,mA,dA,mB,dp,ds) \
PUSH_2(X, DATAp, ds, ds, 0, o, (p), s, X##mB, (dp), \
X##mA, (dA))
#define PUSH_3P(X,o,p,s,mA,dA,mB,dB,mC,dp,ds) \
PUSH_3(X, DATAp, ds, ds, 0, o, (p), s, X##mC, (dp), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_1P(X,o,p,s,mA,dp,ds) \
PUSH_1(X, DATAp, ds, 0, o, (p), s, X##mA, (dp))
#define PUSH_2P(X,o,p,s,mA,dA,mB,dp,ds) \
PUSH_2(X, DATAp, ds, 0, o, (p), s, X##mB, (dp), \
X##mA, (dA))
#define PUSH_3P(X,o,p,s,mA,dA,mB,dB,mC,dp,ds) \
PUSH_3(X, DATAp, ds, 0, o, (p), s, X##mC, (dp), \
X##mB, (dB), \
X##mA, (dA))
#define PUSH_(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,IMPL,...) IMPL
#define PUSH(A...) PUSH_(A, PUSH_10P, PUSH_10D, \

4
drivers/gpu/drm/nouveau/nouveau_svm.c
View File

@ -315,6 +315,10 @@ nouveau_svmm_init(struct drm_device *dev, void *data,
struct drm_nouveau_svm_init *args = data;
int ret;
/* We need to fail if svm is disabled */
if (!cli->drm->svm)
return -ENOSYS;
/* Allocate tracking for SVM-enabled VMM. */
if (!(svmm = kzalloc(sizeof(*svmm), GFP_KERNEL)))
return -ENOMEM;

8
drivers/gpu/drm/vc4/vc4_hvs.c
View File

@ -620,11 +620,11 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* for now we just allocate globally.
*/
if (!hvs->hvs5)
/* 96kB */
drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
/* 48k words of 2x12-bit pixels */
drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
else
/* 70k words */
drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* 60k words of 4x12-bit pixels */
drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.

11
drivers/gpu/drm/vc4/vc4_plane.c
View File

@ -437,6 +437,7 @@ static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
static u32 vc4_lbm_size(struct drm_plane_state *state)
{
struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
u32 pix_per_line;
u32 lbm;
@ -472,7 +473,11 @@ static u32 vc4_lbm_size(struct drm_plane_state *state)
lbm = pix_per_line * 16;
}
lbm = roundup(lbm, 32);
/* Align it to 64 or 128 (hvs5) bytes */
lbm = roundup(lbm, vc4->hvs->hvs5 ? 128 : 64);
/* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
lbm /= vc4->hvs->hvs5 ? 4 : 2;
return lbm;
}
@ -912,9 +917,9 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
if (!vc4_state->is_unity) {
vc4_dlist_write(vc4_state,
VC4_SET_FIELD(vc4_state->crtc_w,
SCALER_POS1_SCL_WIDTH) |
SCALER5_POS1_SCL_WIDTH) |
VC4_SET_FIELD(vc4_state->crtc_h,
SCALER_POS1_SCL_HEIGHT));
SCALER5_POS1_SCL_HEIGHT));
}
/* Position Word 2: Source Image Size */

19
drivers/i2c/busses/i2c-mt65xx.c
View File

@ -1275,7 +1275,8 @@ static int mtk_i2c_probe(struct platform_device *pdev)
mtk_i2c_clock_disable(i2c);
ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
I2C_DRV_NAME, i2c);
if (ret < 0) {
dev_err(&pdev->dev,
"Request I2C IRQ %d fail\n", irq);
@ -1302,7 +1303,16 @@ static int mtk_i2c_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM_SLEEP
static int mtk_i2c_resume(struct device *dev)
static int mtk_i2c_suspend_noirq(struct device *dev)
{
struct mtk_i2c *i2c = dev_get_drvdata(dev);
i2c_mark_adapter_suspended(&i2c->adap);
return 0;
}
static int mtk_i2c_resume_noirq(struct device *dev)
{
int ret;
struct mtk_i2c *i2c = dev_get_drvdata(dev);
@ -1317,12 +1327,15 @@ static int mtk_i2c_resume(struct device *dev)
mtk_i2c_clock_disable(i2c);
i2c_mark_adapter_resumed(&i2c->adap);
return 0;
}
#endif
static const struct dev_pm_ops mtk_i2c_pm = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
mtk_i2c_resume_noirq)
};
static struct platform_driver mtk_i2c_driver = {

7
drivers/iommu/amd/amd_iommu.h
View File

@ -84,12 +84,9 @@ static inline bool is_rd890_iommu(struct pci_dev *pdev)
(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
}
static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)
static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
{
if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
return false;
return !!(iommu->features & f);
return !!(iommu->features & mask);
}
static inline u64 iommu_virt_to_phys(void *vaddr)

4
drivers/iommu/amd/amd_iommu_types.h
View File

@ -387,6 +387,10 @@
#define IOMMU_CAP_NPCACHE 26
#define IOMMU_CAP_EFR 27
/* IOMMU IVINFO */
#define IOMMU_IVINFO_OFFSET 36
#define IOMMU_IVINFO_EFRSUP BIT(0)
/* IOMMU Feature Reporting Field (for IVHD type 10h */
#define IOMMU_FEAT_GASUP_SHIFT 6

56
drivers/iommu/amd/init.c
View File

@ -257,6 +257,8 @@ static void init_device_table_dma(void);
static bool amd_iommu_pre_enabled = true;
static u32 amd_iommu_ivinfo __initdata;
bool translation_pre_enabled(struct amd_iommu *iommu)
{
return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
@ -296,6 +298,18 @@ int amd_iommu_get_num_iommus(void)
return amd_iommus_present;
}
/*
* For IVHD type 0x11/0x40, EFR is also available via IVHD.
* Default to IVHD EFR since it is available sooner
* (i.e. before PCI init).
*/
static void __init early_iommu_features_init(struct amd_iommu *iommu,
struct ivhd_header *h)
{
if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP)
iommu->features = h->efr_reg;
}
/* Access to l1 and l2 indexed register spaces */
static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
@ -1577,6 +1591,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT))
amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
early_iommu_features_init(iommu, h);
break;
default:
return -EINVAL;
@ -1770,6 +1787,35 @@ static const struct attribute_group *amd_iommu_groups[] = {
NULL,
};
/*
* Note: IVHD 0x11 and 0x40 also contains exact copy
* of the IOMMU Extended Feature Register [MMIO Offset 0030h].
* Default to EFR in IVHD since it is available sooner (i.e. before PCI init).
*/
static void __init late_iommu_features_init(struct amd_iommu *iommu)
{
u64 features;
if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
return;
/* read extended feature bits */
features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
if (!iommu->features) {
iommu->features = features;
return;
}
/*
* Sanity check and warn if EFR values from
* IVHD and MMIO conflict.
*/
if (features != iommu->features)
pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx\n).",
features, iommu->features);
}
static int __init iommu_init_pci(struct amd_iommu *iommu)
{
int cap_ptr = iommu->cap_ptr;
@ -1789,8 +1835,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
amd_iommu_iotlb_sup = false;
/* read extended feature bits */
iommu->features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
late_iommu_features_init(iommu);
if (iommu_feature(iommu, FEATURE_GT)) {
int glxval;
@ -2607,6 +2652,11 @@ static void __init free_dma_resources(void)
free_unity_maps();
}
static void __init ivinfo_init(void *ivrs)
{
amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET));
}
/*
* This is the hardware init function for AMD IOMMU in the system.
* This function is called either from amd_iommu_init or from the interrupt
@ -2661,6 +2711,8 @@ static int __init early_amd_iommu_init(void)
if (ret)
goto out;
ivinfo_init(ivrs_base);
amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);

2
drivers/iommu/intel/dmar.c
View File

@ -1496,7 +1496,7 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
* ECAP.
*/
if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
addr, size_order);

32
drivers/iommu/intel/iommu.c
View File

@ -5440,6 +5440,36 @@ intel_iommu_domain_set_attr(struct iommu_domain *domain,
return ret;
}
static bool domain_use_flush_queue(void)
{
struct dmar_drhd_unit *drhd;
struct intel_iommu *iommu;
bool r = true;
if (intel_iommu_strict)
return false;
/*
* The flush queue implementation does not perform page-selective
* invalidations that are required for efficient TLB flushes in virtual
* environments. The benefit of batching is likely to be much lower than
* the overhead of synchronizing the virtual and physical IOMMU
* page-tables.
*/
rcu_read_lock();
for_each_active_iommu(iommu, drhd) {
if (!cap_caching_mode(iommu->cap))
continue;
pr_warn_once("IOMMU batching is disabled due to virtualization");
r = false;
break;
}
rcu_read_unlock();
return r;
}
static int
intel_iommu_domain_get_attr(struct iommu_domain *domain,
enum iommu_attr attr, void *data)
@ -5450,7 +5480,7 @@ intel_iommu_domain_get_attr(struct iommu_domain *domain,
case IOMMU_DOMAIN_DMA:
switch (attr) {
case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
*(int *)data = !intel_iommu_strict;
*(int *)data = domain_use_flush_queue();
return 0;
default:
return -ENODEV;

3
drivers/leds/Kconfig
View File

@ -928,6 +928,9 @@ config LEDS_ACER_A500
This option enables support for the Power Button LED of
Acer Iconia Tab A500.
comment "Flash and Torch LED drivers"
source "drivers/leds/flash/Kconfig"
comment "LED Triggers"
source "drivers/leds/trigger/Kconfig"

3
drivers/leds/Makefile
View File

@ -103,5 +103,8 @@ obj-$(CONFIG_LEDS_SPI_BYTE) += leds-spi-byte.o
# LED Userspace Drivers
obj-$(CONFIG_LEDS_USER) += uleds.o
# Flash and Torch LED Drivers
obj-$(CONFIG_LEDS_CLASS_FLASH) += flash/
# LED Triggers
obj-$(CONFIG_LEDS_TRIGGERS) += trigger/

15
drivers/leds/flash/Kconfig Normal file
View File

@ -0,0 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
if LEDS_CLASS_FLASH
config LEDS_RT8515
tristate "LED support for Richtek RT8515 flash/torch LED"
depends on GPIOLIB
help
This option enables support for the Richtek RT8515 flash
and torch LEDs found on some mobile phones.
To compile this driver as a module, choose M here: the module
will be called leds-rt8515.
endif # LEDS_CLASS_FLASH

3
drivers/leds/flash/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_LEDS_RT8515) += leds-rt8515.o

397
drivers/leds/flash/leds-rt8515.c Normal file
View File

@ -0,0 +1,397 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* LED driver for Richtek RT8515 flash/torch white LEDs
* found on some Samsung mobile phones.
*
* This is a 1.5A Boost dual channel driver produced around 2011.
*
* The component lacks a datasheet, but in the schematic picture
* from the LG P970 service manual you can see the connections
* from the RT8515 to the LED, with two resistors connected
* from the pins "RFS" and "RTS" to ground.
*
* On the LG P970:
* RFS (resistance flash setting?) is 20 kOhm
* RTS (resistance torch setting?) is 39 kOhm
*
* Some sleuthing finds us the RT9387A which we have a datasheet for:
* https://static5.arrow.com/pdfs/2014/7/27/8/21/12/794/rtt_/manual/94download_ds.jspprt9387a.jspprt9387a.pdf
* This apparently works the same way so in theory this driver
* should cover RT9387A as well. This has not been tested, please
* update the compatibles if you add RT9387A support.
*
* Linus Walleij <linus.walleij@linaro.org>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/led-class-flash.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <media/v4l2-flash-led-class.h>
/* We can provide 15-700 mA out to the LED */
#define RT8515_MIN_IOUT_MA 15
#define RT8515_MAX_IOUT_MA 700
/* The maximum intensity is 1-16 for flash and 1-100 for torch */
#define RT8515_FLASH_MAX 16
#define RT8515_TORCH_MAX 100
#define RT8515_TIMEOUT_US 250000U
#define RT8515_MAX_TIMEOUT_US 300000U
struct rt8515 {
struct led_classdev_flash fled;
struct device *dev;
struct v4l2_flash *v4l2_flash;
struct mutex lock;
struct regulator *reg;
struct gpio_desc *enable_torch;
struct gpio_desc *enable_flash;
struct timer_list powerdown_timer;
u32 max_timeout; /* Flash max timeout */
int flash_max_intensity;
int torch_max_intensity;
};
static struct rt8515 *to_rt8515(struct led_classdev_flash *fled)
{
return container_of(fled, struct rt8515, fled);
}
static void rt8515_gpio_led_off(struct rt8515 *rt)
{
gpiod_set_value(rt->enable_flash, 0);
gpiod_set_value(rt->enable_torch, 0);
}
static void rt8515_gpio_brightness_commit(struct gpio_desc *gpiod,
int brightness)
{
int i;
/*
* Toggling a GPIO line with a small delay increases the
* brightness one step at a time.
*/
for (i = 0; i < brightness; i++) {
gpiod_set_value(gpiod, 0);
udelay(1);
gpiod_set_value(gpiod, 1);
udelay(1);
}
}
/* This is setting the torch light level */
static int rt8515_led_brightness_set(struct led_classdev *led,
enum led_brightness brightness)
{
struct led_classdev_flash *fled = lcdev_to_flcdev(led);
struct rt8515 *rt = to_rt8515(fled);
mutex_lock(&rt->lock);
if (brightness == LED_OFF) {
/* Off */
rt8515_gpio_led_off(rt);
} else if (brightness < RT8515_TORCH_MAX) {
/* Step it up to movie mode brightness using the flash pin */
rt8515_gpio_brightness_commit(rt->enable_torch, brightness);
} else {
/* Max torch brightness requested */
gpiod_set_value(rt->enable_torch, 1);
}
mutex_unlock(&rt->lock);
return 0;
}
static int rt8515_led_flash_strobe_set(struct led_classdev_flash *fled,
bool state)
{
struct rt8515 *rt = to_rt8515(fled);
struct led_flash_setting *timeout = &fled->timeout;
int brightness = rt->flash_max_intensity;
mutex_lock(&rt->lock);
if (state) {
/* Enable LED flash mode and set brightness */
rt8515_gpio_brightness_commit(rt->enable_flash, brightness);
/* Set timeout */
mod_timer(&rt->powerdown_timer,
jiffies + usecs_to_jiffies(timeout->val));
} else {
del_timer_sync(&rt->powerdown_timer);
/* Turn the LED off */
rt8515_gpio_led_off(rt);
}
fled->led_cdev.brightness = LED_OFF;
/* After this the torch LED will be disabled */
mutex_unlock(&rt->lock);
return 0;
}
static int rt8515_led_flash_strobe_get(struct led_classdev_flash *fled,
bool *state)
{
struct rt8515 *rt = to_rt8515(fled);
*state = timer_pending(&rt->powerdown_timer);
return 0;
}
static int rt8515_led_flash_timeout_set(struct led_classdev_flash *fled,
u32 timeout)
{
/* The timeout is stored in the led-class-flash core */
return 0;
}
static const struct led_flash_ops rt8515_flash_ops = {
.strobe_set = rt8515_led_flash_strobe_set,
.strobe_get = rt8515_led_flash_strobe_get,
.timeout_set = rt8515_led_flash_timeout_set,
};
static void rt8515_powerdown_timer(struct timer_list *t)
{
struct rt8515 *rt = from_timer(rt, t, powerdown_timer);
/* Turn the LED off */
rt8515_gpio_led_off(rt);
}
static void rt8515_init_flash_timeout(struct rt8515 *rt)
{
struct led_classdev_flash *fled = &rt->fled;
struct led_flash_setting *s;
/* Init flash timeout setting */
s = &fled->timeout;
s->min = 1;
s->max = rt->max_timeout;
s->step = 1;
/*
* Set default timeout to RT8515_TIMEOUT_US except if
* max_timeout from DT is lower.
*/
s->val = min(rt->max_timeout, RT8515_TIMEOUT_US);
}
#if IS_ENABLED(CONFIG_V4L2_FLASH_LED_CLASS)
/* Configure the V2L2 flash subdevice */
static void rt8515_init_v4l2_flash_config(struct rt8515 *rt,
struct v4l2_flash_config *v4l2_sd_cfg)
{
struct led_classdev *led = &rt->fled.led_cdev;
struct led_flash_setting *s;
strscpy(v4l2_sd_cfg->dev_name, led->dev->kobj.name,
sizeof(v4l2_sd_cfg->dev_name));
/*
* Init flash intensity setting: this is a linear scale
* capped from the device tree max intensity setting
* 1..flash_max_intensity
*/
s = &v4l2_sd_cfg->intensity;
s->min = 1;
s->max = rt->flash_max_intensity;
s->step = 1;
s->val = s->max;
}
static void rt8515_v4l2_flash_release(struct rt8515 *rt)
{
v4l2_flash_release(rt->v4l2_flash);
}
#else
static void rt8515_init_v4l2_flash_config(struct rt8515 *rt,
struct v4l2_flash_config *v4l2_sd_cfg)
{
}
static void rt8515_v4l2_flash_release(struct rt8515 *rt)
{
}
#endif
static void rt8515_determine_max_intensity(struct rt8515 *rt,
struct fwnode_handle *led,
const char *resistance,
const char *max_ua_prop, int hw_max,
int *max_intensity_setting)
{
u32 res = 0; /* Can't be 0 so 0 is undefined */
u32 ua;
u32 max_ma;
int max_intensity;
int ret;
fwnode_property_read_u32(rt->dev->fwnode, resistance, &res);
ret = fwnode_property_read_u32(led, max_ua_prop, &ua);
/* Missing info in DT, OK go with hardware maxima */
if (ret || res == 0) {
dev_err(rt->dev,
"either %s or %s missing from DT, using HW max\n",
resistance, max_ua_prop);
max_ma = RT8515_MAX_IOUT_MA;
max_intensity = hw_max;
goto out_assign_max;
}
/*
* Formula from the datasheet, this is the maximum current
* defined by the hardware.
*/
max_ma = (5500 * 1000) / res;
/*
* Calculate max intensity (linear scaling)
* Formula is ((ua / 1000) / max_ma) * 100, then simplified
*/
max_intensity = (ua / 10) / max_ma;
dev_info(rt->dev,
"current restricted from %u to %u mA, max intensity %d/100\n",
max_ma, (ua / 1000), max_intensity);
out_assign_max:
dev_info(rt->dev, "max intensity %d/%d = %d mA\n",
max_intensity, hw_max, max_ma);
*max_intensity_setting = max_intensity;
}
static int rt8515_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct fwnode_handle *child;
struct rt8515 *rt;
struct led_classdev *led;
struct led_classdev_flash *fled;
struct led_init_data init_data = {};
struct v4l2_flash_config v4l2_sd_cfg = {};
int ret;
rt = devm_kzalloc(dev, sizeof(*rt), GFP_KERNEL);
if (!rt)
return -ENOMEM;
rt->dev = dev;
fled = &rt->fled;
led = &fled->led_cdev;
/* ENF - Enable Flash line */
rt->enable_flash = devm_gpiod_get(dev, "enf", GPIOD_OUT_LOW);
if (IS_ERR(rt->enable_flash))
return dev_err_probe(dev, PTR_ERR(rt->enable_flash),
"cannot get ENF (enable flash) GPIO\n");
/* ENT - Enable Torch line */
rt->enable_torch = devm_gpiod_get(dev, "ent", GPIOD_OUT_LOW);
if (IS_ERR(rt->enable_torch))
return dev_err_probe(dev, PTR_ERR(rt->enable_torch),
"cannot get ENT (enable torch) GPIO\n");
child = fwnode_get_next_available_child_node(dev->fwnode, NULL);
if (!child) {
dev_err(dev,
"No fwnode child node found for connected LED.\n");
return -EINVAL;
}
init_data.fwnode = child;
rt8515_determine_max_intensity(rt, child, "richtek,rfs-ohms",
"flash-max-microamp",
RT8515_FLASH_MAX,
&rt->flash_max_intensity);
rt8515_determine_max_intensity(rt, child, "richtek,rts-ohms",
"led-max-microamp",
RT8515_TORCH_MAX,
&rt->torch_max_intensity);
ret = fwnode_property_read_u32(child, "flash-max-timeout-us",
&rt->max_timeout);
if (ret) {
rt->max_timeout = RT8515_MAX_TIMEOUT_US;
dev_warn(dev,
"flash-max-timeout-us property missing\n");
}
timer_setup(&rt->powerdown_timer, rt8515_powerdown_timer, 0);
rt8515_init_flash_timeout(rt);
fled->ops = &rt8515_flash_ops;
led->max_brightness = rt->torch_max_intensity;
led->brightness_set_blocking = rt8515_led_brightness_set;
led->flags |= LED_CORE_SUSPENDRESUME | LED_DEV_CAP_FLASH;
mutex_init(&rt->lock);
platform_set_drvdata(pdev, rt);
ret = devm_led_classdev_flash_register_ext(dev, fled, &init_data);
if (ret) {
dev_err(dev, "can't register LED %s\n", led->name);
mutex_destroy(&rt->lock);
return ret;
}
rt8515_init_v4l2_flash_config(rt, &v4l2_sd_cfg);
/* Create a V4L2 Flash device if V4L2 flash is enabled */
rt->v4l2_flash = v4l2_flash_init(dev, child, fled, NULL, &v4l2_sd_cfg);
if (IS_ERR(rt->v4l2_flash)) {
ret = PTR_ERR(rt->v4l2_flash);
dev_err(dev, "failed to register V4L2 flash device (%d)\n",
ret);
/*
* Continue without the V4L2 flash
* (we still have the classdev)
*/
}
return 0;
}
static int rt8515_remove(struct platform_device *pdev)
{
struct rt8515 *rt = platform_get_drvdata(pdev);
rt8515_v4l2_flash_release(rt);
del_timer_sync(&rt->powerdown_timer);
mutex_destroy(&rt->lock);
return 0;
}
static const struct of_device_id rt8515_match[] = {
{ .compatible = "richtek,rt8515", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rt8515_match);
static struct platform_driver rt8515_driver = {
.driver = {
.name = "rt8515",
.of_match_table = rt8515_match,
},
.probe = rt8515_probe,
.remove = rt8515_remove,
};
module_platform_driver(rt8515_driver);
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("Richtek RT8515 LED driver");
MODULE_LICENSE("GPL");

10
drivers/leds/led-triggers.c
View File

@ -378,14 +378,15 @@ void led_trigger_event(struct led_trigger *trig,
enum led_brightness brightness)
{
struct led_classdev *led_cdev;
unsigned long flags;
if (!trig)
return;
read_lock(&trig->leddev_list_lock);
read_lock_irqsave(&trig->leddev_list_lock, flags);
list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list)
led_set_brightness(led_cdev, brightness);
read_unlock(&trig->leddev_list_lock);
read_unlock_irqrestore(&trig->leddev_list_lock, flags);
}
EXPORT_SYMBOL_GPL(led_trigger_event);
@ -396,11 +397,12 @@ static void led_trigger_blink_setup(struct led_trigger *trig,
int invert)
{
struct led_classdev *led_cdev;
unsigned long flags;
if (!trig)
return;
read_lock(&trig->leddev_list_lock);
read_lock_irqsave(&trig->leddev_list_lock, flags);
list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) {
if (oneshot)
led_blink_set_oneshot(led_cdev, delay_on, delay_off,
@ -408,7 +410,7 @@ static void led_trigger_blink_setup(struct led_trigger *trig,
else
led_blink_set(led_cdev, delay_on, delay_off);
}
read_unlock(&trig->leddev_list_lock);
read_unlock_irqrestore(&trig->leddev_list_lock, flags);
}
void led_trigger_blink(struct led_trigger *trig,

6
drivers/leds/leds-ariel.c
View File

@ -96,14 +96,14 @@ static int ariel_led_probe(struct platform_device *pdev)
return -ENOMEM;
leds[0].ec_index = EC_BLUE_LED;
leds[0].led_cdev.name = "blue:power",
leds[0].led_cdev.name = "blue:power";
leds[0].led_cdev.default_trigger = "default-on";
leds[1].ec_index = EC_AMBER_LED;
leds[1].led_cdev.name = "amber:status",
leds[1].led_cdev.name = "amber:status";
leds[2].ec_index = EC_GREEN_LED;
leds[2].led_cdev.name = "green:status",
leds[2].led_cdev.name = "green:status";
leds[2].led_cdev.default_trigger = "default-on";
for (i = 0; i < NLEDS; i++) {

2
drivers/leds/leds-lm3533.c
View File

@ -679,7 +679,7 @@ static int lm3533_led_probe(struct platform_device *pdev)
led->cdev.brightness_get = lm3533_led_get;
led->cdev.blink_set = lm3533_led_blink_set;
led->cdev.brightness = LED_OFF;
led->cdev.groups = lm3533_led_attribute_groups,
led->cdev.groups = lm3533_led_attribute_groups;
led->id = pdev->id;
mutex_init(&led->mutex);

6
drivers/md/bcache/features.h
View File

@ -33,6 +33,8 @@
#define BCH_FEATURE_COMPAT_FUNCS(name, flagname) \
static inline int bch_has_feature_##name(struct cache_sb *sb) \
{ \
if (sb->version < BCACHE_SB_VERSION_CDEV_WITH_FEATURES) \
return 0; \
return (((sb)->feature_compat & \
BCH##_FEATURE_COMPAT_##flagname) != 0); \
} \
@ -50,6 +52,8 @@ static inline void bch_clear_feature_##name(struct cache_sb *sb) \
#define BCH_FEATURE_RO_COMPAT_FUNCS(name, flagname) \
static inline int bch_has_feature_##name(struct cache_sb *sb) \
{ \
if (sb->version < BCACHE_SB_VERSION_CDEV_WITH_FEATURES) \
return 0; \
return (((sb)->feature_ro_compat & \
BCH##_FEATURE_RO_COMPAT_##flagname) != 0); \
} \
@ -67,6 +71,8 @@ static inline void bch_clear_feature_##name(struct cache_sb *sb) \
#define BCH_FEATURE_INCOMPAT_FUNCS(name, flagname) \
static inline int bch_has_feature_##name(struct cache_sb *sb) \
{ \
if (sb->version < BCACHE_SB_VERSION_CDEV_WITH_FEATURES) \
return 0; \
return (((sb)->feature_incompat & \
BCH##_FEATURE_INCOMPAT_##flagname) != 0); \
} \

21
drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
View File

@ -104,6 +104,7 @@
struct rkisp1_match_data {
const char * const *clks;
unsigned int size;
enum rkisp1_cif_isp_version isp_ver;
};
/* ----------------------------------------------------------------------------
@ -411,15 +412,16 @@ static const char * const rk3399_isp_clks[] = {
"hclk",
};
static const struct rkisp1_match_data rk3399_isp_clk_data = {
static const struct rkisp1_match_data rk3399_isp_match_data = {
.clks = rk3399_isp_clks,
.size = ARRAY_SIZE(rk3399_isp_clks),
.isp_ver = RKISP1_V10,
};
static const struct of_device_id rkisp1_of_match[] = {
{
.compatible = "rockchip,rk3399-cif-isp",
.data = &rk3399_isp_clk_data,
.data = &rk3399_isp_match_data,
},
{},
};
@ -457,15 +459,15 @@ static void rkisp1_debug_init(struct rkisp1_device *rkisp1)
static int rkisp1_probe(struct platform_device *pdev)
{
const struct rkisp1_match_data *clk_data;
const struct rkisp1_match_data *match_data;
struct device *dev = &pdev->dev;
struct rkisp1_device *rkisp1;
struct v4l2_device *v4l2_dev;
unsigned int i;
int ret, irq;
clk_data = of_device_get_match_data(&pdev->dev);
if (!clk_data)
match_data = of_device_get_match_data(&pdev->dev);
if (!match_data)
return -ENODEV;
rkisp1 = devm_kzalloc(dev, sizeof(*rkisp1), GFP_KERNEL);
@ -494,15 +496,16 @@ static int rkisp1_probe(struct platform_device *pdev)
rkisp1->irq = irq;
for (i = 0; i < clk_data->size; i++)
rkisp1->clks[i].id = clk_data->clks[i];
ret = devm_clk_bulk_get(dev, clk_data->size, rkisp1->clks);
for (i = 0; i < match_data->size; i++)
rkisp1->clks[i].id = match_data->clks[i];
ret = devm_clk_bulk_get(dev, match_data->size, rkisp1->clks);
if (ret)
return ret;
rkisp1->clk_size = clk_data->size;
rkisp1->clk_size = match_data->size;
pm_runtime_enable(&pdev->dev);
rkisp1->media_dev.hw_revision = match_data->isp_ver;
strscpy(rkisp1->media_dev.model, RKISP1_DRIVER_NAME,
sizeof(rkisp1->media_dev.model));
rkisp1->media_dev.dev = &pdev->dev;

5
drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
View File

@ -391,7 +391,7 @@ static void rkisp1_goc_config(struct rkisp1_params *params,
RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES; i++)
for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10; i++)
rkisp1_write(params->rkisp1, arg->gamma_y[i],
RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
}
@ -589,7 +589,6 @@ static void rkisp1_hst_config(struct rkisp1_params *params,
RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
RKISP1_CIF_ISP_HIST_WEIGHT_44,
};
const u8 *weight;
unsigned int i;
@ -622,6 +621,8 @@ static void rkisp1_hst_config(struct rkisp1_params *params,
weight[2],
weight[3]),
hist_weight_regs[i]);
rkisp1_write(params->rkisp1, weight[0] & 0x1F, RKISP1_CIF_ISP_HIST_WEIGHT_44);
}
static void

1
drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
View File

@ -365,6 +365,7 @@
#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER 0x0000007F
#define RKISP1_CIF_ISP_HIST_ROW_NUM 5
#define RKISP1_CIF_ISP_HIST_COLUMN_NUM 5
#define RKISP1_CIF_ISP_HIST_GET_BIN(x) ((x) & 0x000FFFFF)
/* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
#define RKISP1_ISP_AFM_CTRL_ENABLE BIT(0)

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