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mlxsw: reg: Add link aggregation configuration registers definitions
Add definitions of SLDR, SLCR2, SLCOR registers that are used to configure LAG. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko
David S. Miller
parent
d2292e8761
commit
d1d40be084
@ -865,6 +865,293 @@ static inline void mlxsw_reg_sftr_pack(char *payload,
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mlxsw_reg_sftr_port_mask_set(payload, port, 1);
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}
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/* SLDR - Switch LAG Descriptor Register
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* -----------------------------------------
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* The switch LAG descriptor register is populated by LAG descriptors.
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* Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
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* max_lag-1.
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*/
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#define MLXSW_REG_SLDR_ID 0x2014
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#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
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static const struct mlxsw_reg_info mlxsw_reg_sldr = {
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.id = MLXSW_REG_SLDR_ID,
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.len = MLXSW_REG_SLDR_LEN,
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};
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enum mlxsw_reg_sldr_op {
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/* Indicates a creation of a new LAG-ID, lag_id must be valid */
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MLXSW_REG_SLDR_OP_LAG_CREATE,
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MLXSW_REG_SLDR_OP_LAG_DESTROY,
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/* Ports that appear in the list have the Distributor enabled */
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MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
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/* Removes ports from the disributor list */
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MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
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};
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/* reg_sldr_op
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* Operation.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
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/* reg_sldr_lag_id
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* LAG identifier. The lag_id is the index into the LAG descriptor table.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
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static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
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{
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MLXSW_REG_ZERO(sldr, payload);
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mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
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mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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}
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static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
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{
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MLXSW_REG_ZERO(sldr, payload);
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mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
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mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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}
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/* reg_sldr_num_ports
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* The number of member ports of the LAG.
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* Reserved for Create / Destroy operations
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* For Add / Remove operations - indicates the number of ports in the list.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
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/* reg_sldr_system_port
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* System port.
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
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static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
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u8 local_port)
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{
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MLXSW_REG_ZERO(sldr, payload);
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mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
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mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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mlxsw_reg_sldr_num_ports_set(payload, 1);
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mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
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}
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static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
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u8 local_port)
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{
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MLXSW_REG_ZERO(sldr, payload);
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mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
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mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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mlxsw_reg_sldr_num_ports_set(payload, 1);
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mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
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}
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/* SLCR - Switch LAG Configuration 2 Register
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* -------------------------------------------
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* The Switch LAG Configuration register is used for configuring the
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* LAG properties of the switch.
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*/
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#define MLXSW_REG_SLCR_ID 0x2015
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#define MLXSW_REG_SLCR_LEN 0x10
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static const struct mlxsw_reg_info mlxsw_reg_slcr = {
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.id = MLXSW_REG_SLCR_ID,
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.len = MLXSW_REG_SLCR_LEN,
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};
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enum mlxsw_reg_slcr_pp {
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/* Global Configuration (for all ports) */
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MLXSW_REG_SLCR_PP_GLOBAL,
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/* Per port configuration, based on local_port field */
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MLXSW_REG_SLCR_PP_PER_PORT,
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};
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/* reg_slcr_pp
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* Per Port Configuration
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* Note: Reading at Global mode results in reading port 1 configuration.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
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/* reg_slcr_local_port
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* Local port number
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* Supported from CPU port
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* Not supported from router port
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* Reserved when pp = Global Configuration
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* Access: Index
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*/
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MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
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enum mlxsw_reg_slcr_type {
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MLXSW_REG_SLCR_TYPE_CRC, /* default */
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MLXSW_REG_SLCR_TYPE_XOR,
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MLXSW_REG_SLCR_TYPE_RANDOM,
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};
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/* reg_slcr_type
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* Hash type
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* Access: RW
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*/
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MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
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/* Ingress port */
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#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
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/* SMAC - for IPv4 and IPv6 packets */
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#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
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/* SMAC - for non-IP packets */
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#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
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#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
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(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
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MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
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/* DMAC - for IPv4 and IPv6 packets */
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#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
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/* DMAC - for non-IP packets */
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#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
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#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
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(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
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MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
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/* Ethertype - for IPv4 and IPv6 packets */
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#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
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/* Ethertype - for non-IP packets */
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#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
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#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
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(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
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MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
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/* VLAN ID - for IPv4 and IPv6 packets */
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#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
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/* VLAN ID - for non-IP packets */
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#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
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#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
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(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
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MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
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/* Source IP address (can be IPv4 or IPv6) */
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#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
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/* Destination IP address (can be IPv4 or IPv6) */
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#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
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/* TCP/UDP source port */
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#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
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/* TCP/UDP destination port*/
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#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
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/* IPv4 Protocol/IPv6 Next Header */
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#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
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/* IPv6 Flow label */
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#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
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/* SID - FCoE source ID */
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#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
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/* DID - FCoE destination ID */
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#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
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/* OXID - FCoE originator exchange ID */
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#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
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/* Destination QP number - for RoCE packets */
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#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
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/* reg_slcr_lag_hash
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* LAG hashing configuration. This is a bitmask, in which each set
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* bit includes the corresponding item in the LAG hash calculation.
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* The default lag_hash contains SMAC, DMAC, VLANID and
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* Ethertype (for all packet types).
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* Access: RW
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*/
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MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
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static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
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{
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MLXSW_REG_ZERO(slcr, payload);
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mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
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mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
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mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
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}
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/* SLCOR - Switch LAG Collector Register
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* -------------------------------------
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* The Switch LAG Collector register controls the Local Port membership
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* in a LAG and enablement of the collector.
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*/
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#define MLXSW_REG_SLCOR_ID 0x2016
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#define MLXSW_REG_SLCOR_LEN 0x10
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static const struct mlxsw_reg_info mlxsw_reg_slcor = {
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.id = MLXSW_REG_SLCOR_ID,
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.len = MLXSW_REG_SLCOR_LEN,
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};
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enum mlxsw_reg_slcor_col {
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/* Port is added with collector disabled */
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MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
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MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
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MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
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MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
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};
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/* reg_slcor_col
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* Collector configuration
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* Access: RW
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*/
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MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
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/* reg_slcor_local_port
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* Local port number
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* Not supported for CPU port
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* Access: Index
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*/
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MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
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/* reg_slcor_lag_id
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* LAG Identifier. Index into the LAG descriptor table.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
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/* reg_slcor_port_index
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* Port index in the LAG list. Only valid on Add Port to LAG col.
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* Valid range is from 0 to cap_max_lag_members-1
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* Access: RW
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*/
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MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
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static inline void mlxsw_reg_slcor_pack(char *payload,
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u8 local_port, u16 lag_id,
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enum mlxsw_reg_slcor_col col)
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{
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MLXSW_REG_ZERO(slcor, payload);
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mlxsw_reg_slcor_col_set(payload, col);
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mlxsw_reg_slcor_local_port_set(payload, local_port);
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mlxsw_reg_slcor_lag_id_set(payload, lag_id);
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}
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static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
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u8 local_port, u16 lag_id,
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u8 port_index)
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{
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mlxsw_reg_slcor_pack(payload, local_port, lag_id,
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MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
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mlxsw_reg_slcor_port_index_set(payload, port_index);
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}
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static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
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u8 local_port, u16 lag_id)
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{
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mlxsw_reg_slcor_pack(payload, local_port, lag_id,
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MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
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}
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static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
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u8 local_port, u16 lag_id)
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{
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mlxsw_reg_slcor_pack(payload, local_port, lag_id,
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MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
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}
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static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
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u8 local_port, u16 lag_id)
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{
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mlxsw_reg_slcor_pack(payload, local_port, lag_id,
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MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
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}
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/* SPMLR - Switch Port MAC Learning Register
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* -----------------------------------------
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* Controls the Switch MAC learning policy per port.
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@ -2653,6 +2940,12 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "SFGC";
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case MLXSW_REG_SFTR_ID:
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return "SFTR";
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case MLXSW_REG_SLDR_ID:
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return "SLDR";
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case MLXSW_REG_SLCR_ID:
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return "SLCR";
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case MLXSW_REG_SLCOR_ID:
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return "SLCOR";
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case MLXSW_REG_SPMLR_ID:
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return "SPMLR";
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case MLXSW_REG_SVFA_ID:
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