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b43: Add NPHY channel switch code
This adds code and table data for channel switching on NPHYs. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -35,12 +35,78 @@ void b43_nphy_xmitpower(struct b43_wldev *dev)
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{//TODO
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}
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static void b43_chantab_radio_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry *e)
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{
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b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
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b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
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b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
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b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
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b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
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b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
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b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
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b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
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b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
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b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
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b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
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b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
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b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
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b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
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b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
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b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
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b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
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b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
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b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
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b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
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b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
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b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
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}
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static void b43_chantab_phy_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry *e)
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{
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b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
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b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
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b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
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b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
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b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
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b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
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}
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static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
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{
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//TODO
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}
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/* Tune the hardware to a new channel. Don't call this directly.
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* Use b43_radio_selectchannel() */
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void b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
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int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
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{
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const struct b43_nphy_channeltab_entry *tabent;
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//TODO
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tabent = b43_nphy_get_chantabent(dev, channel);
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if (!tabent)
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return -ESRCH;
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//FIXME enable/disable band select upper20 in RXCTL
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if (0 /*FIXME 5Ghz*/)
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b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
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else
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b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
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b43_chantab_radio_upload(dev, tabent);
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udelay(50);
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b43_radio_write16(dev, B2055_VCO_CAL10, 5);
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b43_radio_write16(dev, B2055_VCO_CAL10, 45);
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b43_radio_write16(dev, B2055_VCO_CAL10, 65);
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udelay(300);
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if (0 /*FIXME 5Ghz*/)
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b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
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else
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b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
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b43_chantab_phy_upload(dev, tabent);
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b43_nphy_tx_power_fix(dev);
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return 0;
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}
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static void b43_radio_init2055_pre(struct b43_wldev *dev)
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@ -12,6 +12,7 @@
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#define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
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#define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
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#define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
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#define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
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#define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
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#define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
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#define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
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@ -917,7 +918,7 @@ int b43_phy_initn(struct b43_wldev *dev);
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void b43_nphy_radio_turn_on(struct b43_wldev *dev);
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void b43_nphy_radio_turn_off(struct b43_wldev *dev);
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void b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel);
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int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel);
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void b43_nphy_xmitpower(struct b43_wldev *dev);
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void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna);
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@ -3883,7 +3883,8 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
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struct b43_phy *phy = &dev->phy;
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u16 r8, tmp;
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u16 freq;
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u16 channelcookie;
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u16 channelcookie, savedcookie;
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int err = 0;
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if (channel == 0xFF) {
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switch (phy->type) {
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@ -3910,12 +3911,15 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
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if (0 /*FIXME on 5Ghz */)
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channelcookie |= 0x100;
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//FIXME set 40Mhz flag if required
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savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
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switch (phy->type) {
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case B43_PHYTYPE_A:
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if (channel > 200)
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return -EINVAL;
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if (channel > 200) {
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err = -EINVAL;
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goto out;
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}
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freq = channel2freq_a(channel);
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r8 = b43_radio_read16(dev, 0x0008);
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@ -3964,8 +3968,10 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
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b43_phy_xmitpower(dev); //FIXME correct?
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break;
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case B43_PHYTYPE_G:
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if ((channel < 1) || (channel > 14))
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return -EINVAL;
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if ((channel < 1) || (channel > 14)) {
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err = -EINVAL;
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goto out;
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}
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if (synthetic_pu_workaround)
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b43_synth_pu_workaround(dev, channel);
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@ -3990,7 +3996,9 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
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}
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break;
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case B43_PHYTYPE_N:
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b43_nphy_selectchannel(dev, channel);
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err = b43_nphy_selectchannel(dev, channel);
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if (err)
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goto out;
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break;
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default:
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B43_WARN_ON(1);
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@ -3999,8 +4007,12 @@ int b43_radio_selectchannel(struct b43_wldev *dev,
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phy->channel = channel;
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/* Wait for the radio to tune to the channel and stabilize. */
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msleep(8);
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return 0;
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out:
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if (err) {
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b43_shm_write16(dev, B43_SHM_SHARED,
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B43_SHM_SH_CHAN, savedcookie);
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}
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return err;
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}
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void b43_radio_turn_on(struct b43_wldev *dev)
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File diff suppressed because it is too large
Load Diff
@ -4,6 +4,46 @@
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#include <linux/types.h>
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struct b43_nphy_channeltab_entry {
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/* The channel number */
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u8 channel;
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/* Radio register values on channelswitch */
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u8 radio_pll_ref;
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u8 radio_rf_pllmod0;
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u8 radio_rf_pllmod1;
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u8 radio_vco_captail;
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u8 radio_vco_cal1;
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u8 radio_vco_cal2;
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u8 radio_pll_lfc1;
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u8 radio_pll_lfr1;
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u8 radio_pll_lfc2;
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u8 radio_lgbuf_cenbuf;
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u8 radio_lgen_tune1;
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u8 radio_lgen_tune2;
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u8 radio_c1_lgbuf_atune;
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u8 radio_c1_lgbuf_gtune;
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u8 radio_c1_rx_rfr1;
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u8 radio_c1_tx_pgapadtn;
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u8 radio_c1_tx_mxbgtrim;
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u8 radio_c2_lgbuf_atune;
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u8 radio_c2_lgbuf_gtune;
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u8 radio_c2_rx_rfr1;
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u8 radio_c2_tx_pgapadtn;
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u8 radio_c2_tx_mxbgtrim;
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/* PHY register values on channelswitch */
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u16 phy_bw1a;
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u16 phy_bw2;
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u16 phy_bw3;
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u16 phy_bw4;
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u16 phy_bw5;
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u16 phy_bw6;
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/* The channel frequency in MHz */
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u16 freq;
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/* An unknown value */
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u16 unk2;
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};
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struct b43_wldev;
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/* Upload the default register value table.
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@ -14,4 +54,10 @@ void b2055_upload_inittab(struct b43_wldev *dev,
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bool ghz5, bool ignore_uploadflag);
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/* Get the NPHY Channel Switch Table entry for a channel number.
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* Returns NULL on failure to find an entry. */
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const struct b43_nphy_channeltab_entry *
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b43_nphy_get_chantabent(struct b43_wldev *dev, u8 channel);
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#endif /* B43_TABLES_NPHY_H_ */
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