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clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC

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Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2018-10-21 21:30:51 +03:00 committed by Thierry Reding
parent 514fddba84
commit d14ce174ca
1 changed files with 10 additions and 0 deletions
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10
drivers/clk/tegra/clk-tegra20.c
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@ -800,7 +800,9 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
static void __init tegra20_emc_clk_init(void)
{
const u32 use_pllm_ud = BIT(29);
struct clk *clk;
u32 emc_reg;
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
ARRAY_SIZE(mux_pllmcp_clkm),
@ -812,6 +814,14 @@ static void __init tegra20_emc_clk_init(void)
&emc_lock);
clks[TEGRA20_CLK_MC] = clk;
/* un-divided pll_m_out0 is currently unsupported */
emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC);
if (emc_reg & use_pllm_ud) {
pr_err("%s: un-divided PllM_out0 used as clock source\n",
__func__);
return;
}
/*
* Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
* the same time due to a HW bug, this won't happen because we're