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pinctrl: mlxbf3: Add pinctrl driver support
NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs or take the default hardware functionality. Add a driver for the pin muxing. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Asmaa Mnebhi
Linus Walleij
parent
cae630bf47
commit
d11f932808
@ -523,6 +523,19 @@ config PINCTRL_ZYNQMP
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This driver can also be built as a module. If so, the module
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will be called pinctrl-zynqmp.
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config PINCTRL_MLXBF3
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tristate "NVIDIA BlueField-3 SoC Pinctrl driver"
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depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST
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select PINMUX
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select GPIO_MLXBF3
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help
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Say Y to select the pinctrl driver for BlueField-3 SoCs.
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This pin controller allows selecting the mux function for
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each pin. This driver can also be built as a module called
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pinctrl-mlxbf3.
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source "drivers/pinctrl/actions/Kconfig"
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source "drivers/pinctrl/aspeed/Kconfig"
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source "drivers/pinctrl/bcm/Kconfig"
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@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o
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obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o
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obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
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obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
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obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o
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obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
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obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
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obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
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320
drivers/pinctrl/pinctrl-mlxbf3.c
Normal file
320
drivers/pinctrl/pinctrl-mlxbf3.c
Normal file
@ -0,0 +1,320 @@
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// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause
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/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#define MLXBF3_NGPIOS_GPIO0 32
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#define MLXBF3_MAX_GPIO_PINS 56
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enum {
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MLXBF3_GPIO_HW_MODE,
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MLXBF3_GPIO_SW_MODE,
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};
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struct mlxbf3_pinctrl {
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void __iomem *fw_ctrl_set0;
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void __iomem *fw_ctrl_clr0;
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void __iomem *fw_ctrl_set1;
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void __iomem *fw_ctrl_clr1;
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struct device *dev;
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struct pinctrl_dev *pctl;
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struct pinctrl_gpio_range gpio_range;
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};
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#define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
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{ \
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.name = "mlxbf3_gpio_range", \
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.id = _id, \
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.base = _gpiobase, \
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.pin_base = _pinbase, \
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.npins = _npins, \
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}
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static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = {
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MLXBF3_GPIO_RANGE(0, 0, 480, 32),
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MLXBF3_GPIO_RANGE(1, 32, 456, 24),
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};
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static const struct pinctrl_pin_desc mlxbf3_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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PINCTRL_PIN(8, "gpio8"),
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PINCTRL_PIN(9, "gpio9"),
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PINCTRL_PIN(10, "gpio10"),
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PINCTRL_PIN(11, "gpio11"),
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PINCTRL_PIN(12, "gpio12"),
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PINCTRL_PIN(13, "gpio13"),
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PINCTRL_PIN(14, "gpio14"),
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PINCTRL_PIN(15, "gpio15"),
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PINCTRL_PIN(16, "gpio16"),
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PINCTRL_PIN(17, "gpio17"),
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PINCTRL_PIN(18, "gpio18"),
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PINCTRL_PIN(19, "gpio19"),
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PINCTRL_PIN(20, "gpio20"),
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PINCTRL_PIN(21, "gpio21"),
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PINCTRL_PIN(22, "gpio22"),
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PINCTRL_PIN(23, "gpio23"),
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PINCTRL_PIN(24, "gpio24"),
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PINCTRL_PIN(25, "gpio25"),
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PINCTRL_PIN(26, "gpio26"),
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PINCTRL_PIN(27, "gpio27"),
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PINCTRL_PIN(28, "gpio28"),
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PINCTRL_PIN(29, "gpio29"),
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PINCTRL_PIN(30, "gpio30"),
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PINCTRL_PIN(31, "gpio31"),
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PINCTRL_PIN(32, "gpio32"),
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PINCTRL_PIN(33, "gpio33"),
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PINCTRL_PIN(34, "gpio34"),
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PINCTRL_PIN(35, "gpio35"),
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PINCTRL_PIN(36, "gpio36"),
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PINCTRL_PIN(37, "gpio37"),
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PINCTRL_PIN(38, "gpio38"),
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PINCTRL_PIN(39, "gpio39"),
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PINCTRL_PIN(40, "gpio40"),
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PINCTRL_PIN(41, "gpio41"),
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PINCTRL_PIN(42, "gpio42"),
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PINCTRL_PIN(43, "gpio43"),
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PINCTRL_PIN(44, "gpio44"),
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PINCTRL_PIN(45, "gpio45"),
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PINCTRL_PIN(46, "gpio46"),
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PINCTRL_PIN(47, "gpio47"),
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PINCTRL_PIN(48, "gpio48"),
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PINCTRL_PIN(49, "gpio49"),
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PINCTRL_PIN(50, "gpio50"),
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PINCTRL_PIN(51, "gpio51"),
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PINCTRL_PIN(52, "gpio52"),
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PINCTRL_PIN(53, "gpio53"),
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PINCTRL_PIN(54, "gpio54"),
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PINCTRL_PIN(55, "gpio55"),
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};
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/*
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* All single-pin functions can be mapped to any GPIO, however pinmux applies
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* functions to pin groups and only those groups declared as supporting that
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* function. To make this work we must put each pin in its own dummy group so
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* that the functions can be described as applying to all pins.
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* We use the same name as in the datasheet.
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*/
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static const char * const mlxbf3_pinctrl_single_group_names[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
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"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
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"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
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"gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
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"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
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"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
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};
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static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev)
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{
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/* Number single-pin groups */
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return MLXBF3_MAX_GPIO_PINS;
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}
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static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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return mlxbf3_pinctrl_single_group_names[selector];
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}
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static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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/* return the dummy group for a single pin */
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*pins = &selector;
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*num_pins = 1;
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return 0;
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}
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static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = {
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.get_groups_count = mlxbf3_get_groups_count,
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.get_group_name = mlxbf3_get_group_name,
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.get_group_pins = mlxbf3_get_group_pins,
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};
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/*
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* Only 2 functions are supported and they apply to all pins:
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* 1) Default hardware functionality
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* 2) Software controlled GPIO
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*/
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static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" };
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static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" };
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struct pinfunction mlxbf3_pmx_funcs[] = {
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PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1),
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PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1),
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};
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static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(mlxbf3_pmx_funcs);
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}
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static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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return mlxbf3_pmx_funcs[selector].name;
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}
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static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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*groups = mlxbf3_pmx_funcs[selector].groups;
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*num_groups = MLXBF3_MAX_GPIO_PINS;
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return 0;
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}
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static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev,
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unsigned int selector,
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unsigned int group)
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{
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struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
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if (selector == MLXBF3_GPIO_HW_MODE) {
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if (group < MLXBF3_NGPIOS_GPIO0)
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writel(BIT(group), priv->fw_ctrl_clr0);
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else
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writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
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}
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if (selector == MLXBF3_GPIO_SW_MODE) {
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if (group < MLXBF3_NGPIOS_GPIO0)
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writel(BIT(group), priv->fw_ctrl_set0);
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else
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writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
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}
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return 0;
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}
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static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
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if (offset < MLXBF3_NGPIOS_GPIO0)
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writel(BIT(offset), priv->fw_ctrl_set0);
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else
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writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
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return 0;
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}
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static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
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/* disable GPIO functionality by giving control back to hardware */
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if (offset < MLXBF3_NGPIOS_GPIO0)
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writel(BIT(offset), priv->fw_ctrl_clr0);
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else
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writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
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}
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static const struct pinmux_ops mlxbf3_pmx_ops = {
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.get_functions_count = mlxbf3_pmx_get_funcs_count,
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.get_function_name = mlxbf3_pmx_get_func_name,
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.get_function_groups = mlxbf3_pmx_get_groups,
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.set_mux = mlxbf3_pmx_set,
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.gpio_request_enable = mlxbf3_gpio_request_enable,
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.gpio_disable_free = mlxbf3_gpio_disable_free,
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};
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static struct pinctrl_desc mlxbf3_pin_desc = {
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.name = "pinctrl-mlxbf3",
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.pins = mlxbf3_pins,
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.npins = ARRAY_SIZE(mlxbf3_pins),
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.pctlops = &mlxbf3_pinctrl_group_ops,
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.pmxops = &mlxbf3_pmx_ops,
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.owner = THIS_MODULE,
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};
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static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS);
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static int mlxbf3_pinctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mlxbf3_pinctrl *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = &pdev->dev;
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priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->fw_ctrl_set0))
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return PTR_ERR(priv->fw_ctrl_set0);
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priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(priv->fw_ctrl_set0))
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return PTR_ERR(priv->fw_ctrl_set0);
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priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
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if (IS_ERR(priv->fw_ctrl_set0))
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return PTR_ERR(priv->fw_ctrl_set0);
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priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
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if (IS_ERR(priv->fw_ctrl_set0))
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return PTR_ERR(priv->fw_ctrl_set0);
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ret = devm_pinctrl_register_and_init(dev,
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&mlxbf3_pin_desc,
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priv,
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&priv->pctl);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
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ret = pinctrl_enable(priv->pctl);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to enable pinctrl\n");
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pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2);
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return 0;
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}
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static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = {
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{ "MLNXBF34", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids);
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static struct platform_driver mlxbf3_pinctrl_driver = {
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.driver = {
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.name = "pinctrl-mlxbf3",
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.acpi_match_table = mlxbf3_pinctrl_acpi_ids,
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},
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.probe = mlxbf3_pinctrl_probe,
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};
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module_platform_driver(mlxbf3_pinctrl_driver);
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MODULE_DESCRIPTION("NVIDIA pinctrl driver");
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MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
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MODULE_LICENSE("Dual BSD/GPL");
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