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iio: adc: sophgo-saradc: Add driver for Sophgo CV1800B SARADC
This adds a driver for the Sophgo CV1800B SARADC. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Link: https://patch.msgid.link/20240829-sg2002-adc-v5-2-aacb381e869b@bootlin.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Thomas Bonnefille
Jonathan Cameron
parent
cf082dbeda
commit
d1022ff5f9
@ -1192,6 +1192,16 @@ config SC27XX_ADC
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This driver can also be built as a module. If so, the module
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will be called sc27xx_adc.
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config SOPHGO_CV1800B_ADC
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tristate "Sophgo CV1800B SARADC"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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Say yes here to build support for the SARADC integrated inside
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the Sophgo CV1800B SoC.
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This driver can also be built as a module. If so, the module
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will be called sophgo_cv1800b_adc.
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config SPEAR_ADC
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tristate "ST SPEAr ADC"
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depends on PLAT_SPEAR || COMPILE_TEST
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@ -108,6 +108,7 @@ obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
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obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
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obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
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obj-$(CONFIG_SOPHGO_CV1800B_ADC) += sophgo-cv1800b-adc.o
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obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
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obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
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obj-$(CONFIG_STM32_ADC) += stm32-adc.o
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227
drivers/iio/adc/sophgo-cv1800b-adc.c
Normal file
227
drivers/iio/adc/sophgo-cv1800b-adc.c
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@ -0,0 +1,227 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Sophgo CV1800B SARADC Driver
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*
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* Copyright (C) Bootlin 2024
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* Author: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
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*/
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/iio/iio.h>
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#define CV1800B_ADC_CTRL_REG 0x04
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#define CV1800B_ADC_EN BIT(0)
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#define CV1800B_ADC_SEL(x) BIT((x) + 5)
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#define CV1800B_ADC_STATUS_REG 0x08
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#define CV1800B_ADC_BUSY BIT(0)
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#define CV1800B_ADC_CYC_SET_REG 0x0C
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#define CV1800B_MASK_STARTUP_CYCLE GENMASK(4, 0)
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#define CV1800B_MASK_SAMPLE_WINDOW GENMASK(11, 8)
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#define CV1800B_MASK_CLKDIV GENMASK(15, 12)
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#define CV1800B_MASK_COMPARE_CYCLE GENMASK(19, 16)
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#define CV1800B_ADC_CH_RESULT_REG(x) (0x14 + 4 * (x))
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#define CV1800B_ADC_CH_RESULT GENMASK(11, 0)
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#define CV1800B_ADC_CH_VALID BIT(15)
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#define CV1800B_ADC_INTR_EN_REG 0x20
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#define CV1800B_ADC_INTR_CLR_REG 0x24
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#define CV1800B_ADC_INTR_CLR_BIT BIT(0)
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#define CV1800B_ADC_INTR_STA_REG 0x28
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#define CV1800B_ADC_INTR_STA_BIT BIT(0)
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#define CV1800B_READ_TIMEOUT_MS 1000
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#define CV1800B_READ_TIMEOUT_US (CV1800B_READ_TIMEOUT_MS * 1000)
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#define CV1800B_ADC_CHANNEL(index) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
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.scan_index = index, \
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}
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struct cv1800b_adc {
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struct completion completion;
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void __iomem *regs;
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struct mutex lock; /* ADC Control and Result register */
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struct clk *clk;
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int irq;
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};
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static const struct iio_chan_spec sophgo_channels[] = {
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CV1800B_ADC_CHANNEL(0),
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CV1800B_ADC_CHANNEL(1),
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CV1800B_ADC_CHANNEL(2),
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};
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static void cv1800b_adc_start_measurement(struct cv1800b_adc *saradc,
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int channel)
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{
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writel(0, saradc->regs + CV1800B_ADC_CTRL_REG);
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writel(CV1800B_ADC_SEL(channel) | CV1800B_ADC_EN,
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saradc->regs + CV1800B_ADC_CTRL_REG);
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}
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static int cv1800b_adc_wait(struct cv1800b_adc *saradc)
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{
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if (saradc->irq < 0) {
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u32 reg;
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return readl_poll_timeout(saradc->regs + CV1800B_ADC_STATUS_REG,
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reg, !(reg & CV1800B_ADC_BUSY),
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500, CV1800B_READ_TIMEOUT_US);
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}
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return wait_for_completion_timeout(&saradc->completion,
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msecs_to_jiffies(CV1800B_READ_TIMEOUT_MS)) > 0 ?
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0 : -ETIMEDOUT;
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}
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static int cv1800b_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct cv1800b_adc *saradc = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW: {
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u32 sample;
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scoped_guard(mutex, &saradc->lock) {
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int ret;
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cv1800b_adc_start_measurement(saradc, chan->scan_index);
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ret = cv1800b_adc_wait(saradc);
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if (ret < 0)
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return ret;
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sample = readl(saradc->regs + CV1800B_ADC_CH_RESULT_REG(chan->scan_index));
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}
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if (!(sample & CV1800B_ADC_CH_VALID))
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return -ENODATA;
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*val = sample & CV1800B_ADC_CH_RESULT;
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return IIO_VAL_INT;
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}
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case IIO_CHAN_INFO_SCALE:
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*val = 3300;
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ: {
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u32 status_reg = readl(saradc->regs + CV1800B_ADC_CYC_SET_REG);
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unsigned int clk_div = (1 + FIELD_GET(CV1800B_MASK_CLKDIV, status_reg));
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unsigned int freq = clk_get_rate(saradc->clk) / clk_div;
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unsigned int nb_startup_cycle = 1 + FIELD_GET(CV1800B_MASK_STARTUP_CYCLE, status_reg);
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unsigned int nb_sample_cycle = 1 + FIELD_GET(CV1800B_MASK_SAMPLE_WINDOW, status_reg);
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unsigned int nb_compare_cycle = 1 + FIELD_GET(CV1800B_MASK_COMPARE_CYCLE, status_reg);
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*val = freq / (nb_startup_cycle + nb_sample_cycle + nb_compare_cycle);
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return IIO_VAL_INT;
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}
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t cv1800b_adc_interrupt_handler(int irq, void *private)
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{
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struct cv1800b_adc *saradc = private;
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u32 reg = readl(saradc->regs + CV1800B_ADC_INTR_STA_REG);
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if (!(FIELD_GET(CV1800B_ADC_INTR_STA_BIT, reg)))
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return IRQ_NONE;
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writel(CV1800B_ADC_INTR_CLR_BIT, saradc->regs + CV1800B_ADC_INTR_CLR_REG);
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complete(&saradc->completion);
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return IRQ_HANDLED;
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}
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static const struct iio_info cv1800b_adc_info = {
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.read_raw = &cv1800b_adc_read_raw,
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};
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static int cv1800b_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cv1800b_adc *saradc;
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struct iio_dev *indio_dev;
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int ret;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*saradc));
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if (!indio_dev)
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return -ENOMEM;
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saradc = iio_priv(indio_dev);
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indio_dev->name = "sophgo-cv1800b-adc";
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->info = &cv1800b_adc_info;
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indio_dev->num_channels = ARRAY_SIZE(sophgo_channels);
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indio_dev->channels = sophgo_channels;
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saradc->clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(saradc->clk))
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return PTR_ERR(saradc->clk);
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saradc->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(saradc->regs))
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return PTR_ERR(saradc->regs);
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saradc->irq = platform_get_irq_optional(pdev, 0);
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if (saradc->irq > 0) {
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init_completion(&saradc->completion);
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ret = devm_request_irq(dev, saradc->irq,
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cv1800b_adc_interrupt_handler, 0,
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dev_name(dev), saradc);
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if (ret)
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return ret;
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writel(1, saradc->regs + CV1800B_ADC_INTR_EN_REG);
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}
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ret = devm_mutex_init(dev, &saradc->lock);
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if (ret)
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return ret;
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writel(FIELD_PREP(CV1800B_MASK_STARTUP_CYCLE, 15) |
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FIELD_PREP(CV1800B_MASK_SAMPLE_WINDOW, 15) |
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FIELD_PREP(CV1800B_MASK_CLKDIV, 1) |
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FIELD_PREP(CV1800B_MASK_COMPARE_CYCLE, 15),
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saradc->regs + CV1800B_ADC_CYC_SET_REG);
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return devm_iio_device_register(dev, indio_dev);
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}
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static const struct of_device_id cv1800b_adc_match[] = {
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{ .compatible = "sophgo,cv1800b-saradc", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cv1800b_adc_match);
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static struct platform_driver cv1800b_adc_driver = {
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.driver = {
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.name = "sophgo-cv1800b-saradc",
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.of_match_table = cv1800b_adc_match,
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},
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.probe = cv1800b_adc_probe,
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};
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module_platform_driver(cv1800b_adc_driver);
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MODULE_AUTHOR("Thomas Bonnefille <thomas.bonnefille@bootlin.com>");
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MODULE_DESCRIPTION("Sophgo CV1800B SARADC driver");
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MODULE_LICENSE("GPL");
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