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iommu/exynos: Use exynos-iommu specific typedef
This commit introduces sysmmu_pte_t for page table entries and sysmmu_iova_t vor I/O virtual address that is manipulated by exynos-iommu driver. The purpose of the typedef is to remove dependencies to the driver code from the change of CPU architecture from 32 bit to 64 bit. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Cho KyongHo
Joerg Roedel
parent
9d4e7a24d7
commit
d09d78fc98
@ -29,6 +29,9 @@
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#include <asm/cacheflush.h>
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#include <asm/pgtable.h>
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typedef u32 sysmmu_iova_t;
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typedef u32 sysmmu_pte_t;
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/* We does not consider super section mapping (16MB) */
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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@ -50,20 +53,32 @@
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#define lv2ent_small(pent) ((*(pent) & 2) == 2)
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#define lv2ent_large(pent) ((*(pent) & 3) == 1)
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#define section_phys(sent) (*(sent) & SECT_MASK)
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#define section_offs(iova) ((iova) & 0xFFFFF)
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#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
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#define lpage_offs(iova) ((iova) & 0xFFFF)
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#define spage_phys(pent) (*(pent) & SPAGE_MASK)
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#define spage_offs(iova) ((iova) & 0xFFF)
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static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
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{
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return iova & (size - 1);
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}
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#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
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#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
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#define section_phys(sent) (*(sent) & SECT_MASK)
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#define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
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#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
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#define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
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#define spage_phys(pent) (*(pent) & SPAGE_MASK)
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#define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES 256
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
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static u32 lv1ent_offset(sysmmu_iova_t iova)
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{
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return iova >> SECT_ORDER;
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}
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static u32 lv2ent_offset(sysmmu_iova_t iova)
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{
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return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
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}
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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@ -101,14 +116,14 @@
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static struct kmem_cache *lv2table_kmem_cache;
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static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
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static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
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{
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return pgtable + lv1ent_offset(iova);
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}
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static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
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static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
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{
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return (unsigned long *)phys_to_virt(
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return (sysmmu_pte_t *)phys_to_virt(
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lv2table_base(sent)) + lv2ent_offset(iova);
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}
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@ -150,7 +165,7 @@ static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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struct exynos_iommu_domain {
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struct list_head clients; /* list of sysmmu_drvdata.node */
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unsigned long *pgtable; /* lv1 page table, 16KB */
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sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
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short *lv2entcnt; /* free lv2 entry counter for each section */
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spinlock_t lock; /* lock for this structure */
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spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
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@ -215,7 +230,7 @@ static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
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}
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static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
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unsigned long iova, unsigned int num_inv)
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sysmmu_iova_t iova, unsigned int num_inv)
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{
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unsigned int i;
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for (i = 0; i < num_inv; i++) {
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@ -226,7 +241,7 @@ static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
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}
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static void __sysmmu_set_ptbase(void __iomem *sfrbase,
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unsigned long pgd)
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phys_addr_t pgd)
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{
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__raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
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__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
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@ -236,22 +251,22 @@ static void __sysmmu_set_ptbase(void __iomem *sfrbase,
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static void show_fault_information(const char *name,
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enum exynos_sysmmu_inttype itype,
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phys_addr_t pgtable_base, unsigned long fault_addr)
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phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
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{
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unsigned long *ent;
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sysmmu_pte_t *ent;
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if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
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itype = SYSMMU_FAULT_UNKNOWN;
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pr_err("%s occurred at %#lx by %s(Page table base: %pa)\n",
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pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
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sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
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ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
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pr_err("\tLv1 entry: 0x%lx\n", *ent);
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pr_err("\tLv1 entry: %#x\n", *ent);
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if (lv1ent_page(ent)) {
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ent = page_entry(ent, fault_addr);
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pr_err("\t Lv2 entry: 0x%lx\n", *ent);
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pr_err("\t Lv2 entry: %#x\n", *ent);
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}
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}
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@ -260,7 +275,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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/* SYSMMU is in blocked when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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enum exynos_sysmmu_inttype itype;
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unsigned long addr = -1;
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sysmmu_iova_t addr = -1;
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int ret = -ENOSYS;
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WARN_ON(!is_sysmmu_active(data));
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@ -284,7 +299,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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__func__);
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BUG();
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} else {
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unsigned long base =
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unsigned int base =
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__raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
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show_fault_information(dev_name(data->sysmmu),
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itype, base, addr);
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@ -349,7 +364,7 @@ finish:
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* enabled before.
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*/
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static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
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unsigned long pgtable, struct iommu_domain *domain)
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phys_addr_t pgtable, struct iommu_domain *domain)
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{
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int ret = 0;
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unsigned long flags;
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@ -390,7 +405,7 @@ finish:
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return ret;
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}
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int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
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int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable)
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{
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struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
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int ret;
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@ -426,7 +441,7 @@ static bool exynos_sysmmu_disable(struct device *dev)
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return disabled;
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}
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static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova,
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static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
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size_t size)
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{
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unsigned long flags;
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@ -577,7 +592,7 @@ static int exynos_iommu_domain_init(struct iommu_domain *domain)
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if (!priv)
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return -ENOMEM;
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priv->pgtable = (unsigned long *)__get_free_pages(
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priv->pgtable = (sysmmu_pte_t *)__get_free_pages(
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GFP_KERNEL | __GFP_ZERO, 2);
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if (!priv->pgtable)
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goto err_pgtable;
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@ -716,19 +731,19 @@ finish:
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pm_runtime_put(data->sysmmu);
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}
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static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
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static sysmmu_pte_t *alloc_lv2entry(sysmmu_pte_t *sent, sysmmu_iova_t iova,
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short *pgcounter)
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{
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if (lv1ent_section(sent)) {
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WARN(1, "Trying mapping on %#08lx mapped with 1MiB page", iova);
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WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
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return ERR_PTR(-EADDRINUSE);
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}
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if (lv1ent_fault(sent)) {
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unsigned long *pent;
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sysmmu_pte_t *pent;
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pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
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BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
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BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
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if (!pent)
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return ERR_PTR(-ENOMEM);
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@ -741,18 +756,18 @@ static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
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return page_entry(sent, iova);
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}
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static int lv1set_section(unsigned long *sent, unsigned long iova,
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static int lv1set_section(sysmmu_pte_t *sent, sysmmu_iova_t iova,
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phys_addr_t paddr, short *pgcnt)
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{
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if (lv1ent_section(sent)) {
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WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped",
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WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
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iova);
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return -EADDRINUSE;
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}
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if (lv1ent_page(sent)) {
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if (*pgcnt != NUM_LV2ENTRIES) {
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WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped",
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WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
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iova);
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return -EADDRINUSE;
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}
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@ -768,7 +783,7 @@ static int lv1set_section(unsigned long *sent, unsigned long iova,
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return 0;
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}
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static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
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static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
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short *pgcnt)
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{
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if (size == SPAGE_SIZE) {
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@ -800,11 +815,12 @@ static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
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return 0;
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}
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static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
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static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova,
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phys_addr_t paddr, size_t size, int prot)
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{
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struct exynos_iommu_domain *priv = domain->priv;
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unsigned long *entry;
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sysmmu_pte_t *entry;
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sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
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unsigned long flags;
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int ret = -ENOMEM;
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@ -818,7 +834,7 @@ static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
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ret = lv1set_section(entry, iova, paddr,
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&priv->lv2entcnt[lv1ent_offset(iova)]);
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} else {
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unsigned long *pent;
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sysmmu_pte_t *pent;
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pent = alloc_lv2entry(entry, iova,
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&priv->lv2entcnt[lv1ent_offset(iova)]);
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@ -831,7 +847,7 @@ static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
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}
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if (ret)
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pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
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pr_debug("%s: Failed to map iova %#x/%#zx bytes\n",
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__func__, iova, size);
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spin_unlock_irqrestore(&priv->pgtablelock, flags);
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@ -840,13 +856,14 @@ static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
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}
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static size_t exynos_iommu_unmap(struct iommu_domain *domain,
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unsigned long iova, size_t size)
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unsigned long l_iova, size_t size)
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{
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struct exynos_iommu_domain *priv = domain->priv;
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struct sysmmu_drvdata *data;
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unsigned long flags;
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unsigned long *ent;
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sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
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sysmmu_pte_t *ent;
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size_t err_pgsize;
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unsigned long flags;
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BUG_ON(priv->pgtable == NULL);
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@ -913,7 +930,7 @@ err:
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spin_unlock_irqrestore(&priv->pgtablelock, flags);
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WARN(1,
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"%s: Failed due to size(%#x) @ %#08lx is smaller than page size %#x\n",
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"%s: Failed due to size(%#zx) @ %#x is smaller than page size %#zx\n",
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__func__, size, iova, err_pgsize);
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return 0;
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@ -923,7 +940,7 @@ static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct exynos_iommu_domain *priv = domain->priv;
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unsigned long *entry;
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sysmmu_pte_t *entry;
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unsigned long flags;
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phys_addr_t phys = 0;
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